mirrors/yosys
3
0
Fork 0
mirror of https://github.com/YosysHQ/yosys synced 2026-06-27 02:58:48 +00:00
Code Activity

Remove trailing whitespaces

Browse source
This commit is contained in:
Miodrag Milanovic 2026-06-23 07:24:59 +02:00
parent 48a3dcc02a
commit a689342207
317 changed files with 3136 additions and 3136 deletions
Download patch file Download diff file Expand all files Collapse all files

6
tests/asicworld/code_tidbits_blocking.v
View file

@ -2,16 +2,16 @@ module blocking (clk,a,c);
input clk;
input a;
output c;
wire clk;
wire a;
reg c;
reg b;
always @ (posedge clk )
begin
b = a;
c = b;
end
endmodule