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https://github.com/YosysHQ/yosys
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Remove trailing whitespaces
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parent
48a3dcc02a
commit
a689342207
317 changed files with 3136 additions and 3136 deletions
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@ -1,5 +1,5 @@
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// This file exists to map purely-synchronous flops to ABC9 flops, while
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// mapping flops with asynchronous-set/clear as boxes, this is because ABC9
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// This file exists to map purely-synchronous flops to ABC9 flops, while
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// mapping flops with asynchronous-set/clear as boxes, this is because ABC9
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// doesn't support asynchronous-set/clear flops in sequential synthesis.
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module dffepc (
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@ -180,7 +180,7 @@ struct QlBramMergeWorker {
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};
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struct QlBramMergePass : public Pass {
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QlBramMergePass() : Pass("ql_bram_merge", "Infers QuickLogic k6n10f BRAM pairs that can operate independently") {}
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void help() override
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@ -29,7 +29,7 @@ PRIVATE_NAMESPACE_BEGIN
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struct QlBramTypesPass : public Pass {
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QlBramTypesPass() : Pass("ql_bram_types", "Change TDP36K type to subtypes") {}
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void help() override
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@ -81,7 +81,7 @@ struct QlBramTypesPass : public Pass {
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{
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if (cell->type != ID(TDP36K) || !cell->hasParam(ID(MODE_BITS)))
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continue;
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RTLIL::Const mode_bits = cell->getParam(ID(MODE_BITS));
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bool split = mode_bits.extract(80).as_bool();
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@ -139,7 +139,7 @@ struct QlBramTypesPass : public Pass {
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type += "SYNC_";
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else
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type += "ASYNC_";
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} else
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} else
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type += "_BRAM_";
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if (split) {
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@ -15,7 +15,7 @@
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// SPDX-License-Identifier: Apache-2.0
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module \$__QLF_TDP36K (PORT_A_CLK, PORT_A_ADDR, PORT_A_WR_DATA, PORT_A_WR_EN, PORT_A_WR_BE, PORT_A_CLK_EN, PORT_A_RD_DATA,
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PORT_B_CLK, PORT_B_ADDR, PORT_B_WR_DATA, PORT_B_WR_EN, PORT_B_WR_BE, PORT_B_CLK_EN, PORT_B_RD_DATA);
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PORT_B_CLK, PORT_B_ADDR, PORT_B_WR_DATA, PORT_B_WR_EN, PORT_B_WR_BE, PORT_B_CLK_EN, PORT_B_RD_DATA);
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parameter INIT = 0;
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@ -342,7 +342,7 @@ struct SynthQuickLogicPass : public ScriptPass {
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run("clean");
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run("opt_lut");
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}
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if (check_label("iomap", "(for qlf_k6n10f, skip if -noioff)") && (family == "qlf_k6n10f" || help_mode)) {
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if (ioff || help_mode) {
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run("ql_ioff");
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