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Remove trailing whitespaces

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This commit is contained in:
Miodrag Milanovic 2026-06-23 07:24:59 +02:00
parent 48a3dcc02a
commit a689342207
317 changed files with 3136 additions and 3136 deletions
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36
techlibs/microchip/LSRAM.txt
View file

@ -1,11 +1,11 @@
# ISC License
#
#
# Copyright (C) 2024 Microchip Technology Inc. and its subsidiaries
#
#
# Permission to use, copy, modify, and/or distribute this software for any
# purpose with or without fee is hereby granted, provided that the above
# copyright notice and this permission notice appear in all copies.
#
#
# THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
# WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
# MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
@ -28,9 +28,9 @@ ram block $__LSRAM_TDP_ {
init any;
# port A and port B are allowed to have different widths, but they MUST have
# WIDTH values of the same set.
# WIDTH values of the same set.
# Example: Port A has a Data Width of 1. Then Port B's Data Width must be either
# 1, 2, 4, 8, or 16 (both values are in the 'WIDTH_1' set).
# 1, 2, 4, 8, or 16 (both values are in the 'WIDTH_1' set).
# WIDTH_1 = {1, 2, 4, 8, 16}
# WIDTH_2 = {5, 10, 20}
@ -38,7 +38,7 @@ ram block $__LSRAM_TDP_ {
# "byte" must be larger than width, or width must be a multipler of "byte"
# if "byte" > WIDTH, a single enable wire is inferred
# otherwise, WIDTH/byte number of enable wires are inferred
#
#
# WIDTH = {1, 2, 4, 5, 8, 10} requires 1 enable wire
# WIDTH = {16, 20} requires 2 enable wire
@ -58,7 +58,7 @@ ram block $__LSRAM_TDP_ {
byte 8;
}
option "WIDTH_CONFIG" "ALIGN" {
# Data-Width| Address bits
# 5 | 12
# 10 | 11
@ -72,14 +72,14 @@ ram block $__LSRAM_TDP_ {
widths 5 10 20 per_port;
byte 10;
}
port srsw "A" "B" {
# read & write width must be same
width tied;
# clock polarity is rising
clock posedge;
@ -101,8 +101,8 @@ ram block $__LSRAM_TDP_ {
rdwr no_change;
# Write transparency:
# For write ports, define behaviour when another synchronous read port
# reads from the same memory cell that said write port is writing to at the same time.
# For write ports, define behaviour when another synchronous read port
# reads from the same memory cell that said write port is writing to at the same time.
wrtrans all old;
}
portoption "WRITE_MODE" "WRITE_FIRST" {
@ -123,9 +123,9 @@ ram block $__LSRAM_TDP_ {
# two-port configuration
ram block $__LSRAM_SDP_ {
# since two-port configuration is dedicated for wide-read/write,
# we want to prioritize this configuration over TDP to avoid tool picking multiple TDP RAMs
# we want to prioritize this configuration over TDP to avoid tool picking multiple TDP RAMs
# inplace of a single SDP RAM for wide read/write. This means the cost of a single SDP should
# be less than 2 TDP.
cost 129;
@ -147,10 +147,10 @@ ram block $__LSRAM_SDP_ {
# width = 32, byte-write size is 8, ignore other widths
byte 8;
}
option "WIDTH_CONFIG" "ALIGN" {
# Data-Width| Address bits
# 5 | 12
# 10 | 11
@ -166,7 +166,7 @@ ram block $__LSRAM_SDP_ {
port sw "W" {
# only consider wide write
option "WIDTH_CONFIG" "REGULAR" width 32;
option "WIDTH_CONFIG" "ALIGN" width 40;
@ -174,7 +174,7 @@ ram block $__LSRAM_SDP_ {
# only simple write supported for two-port mode
wrtrans all old;
optional;
}
port sr "R" {

16
techlibs/microchip/LSRAM_map.v
View file

@ -71,7 +71,7 @@ parameter PORT_A_WR_USED = 0;
wire [2:0] A_BLK_SEL = (PORT_A_RD_USED == 1 || PORT_A_WR_USED == 1) ? 3'b111 : 3'b000;
wire [2:0] B_BLK_SEL = (PORT_B_RD_USED == 1 || PORT_B_WR_USED == 1) ? 3'b111 : 3'b000;
// wires for write data
// wires for write data
generate
wire [19:0] A_write_data;
wire [19:0] B_write_data;
@ -115,9 +115,9 @@ wire [2:0] B_width = (PORT_B_WIDTH == 1) ? 3'b000 :
(PORT_B_WIDTH == 8 || PORT_B_WIDTH == 10) ? 3'b011 : 3'b100;
// write modes
wire [1:0] A_write_mode = PORT_A_OPTION_WRITE_MODE == "NO_CHANGE" ? 2'b00 :
wire [1:0] A_write_mode = PORT_A_OPTION_WRITE_MODE == "NO_CHANGE" ? 2'b00 :
PORT_A_OPTION_WRITE_MODE == "WRITE_FIRST" ? 2'b01 : 2'b10;
wire [1:0] B_write_mode = PORT_B_OPTION_WRITE_MODE == "NO_CHANGE" ? 2'b00 :
wire [1:0] B_write_mode = PORT_B_OPTION_WRITE_MODE == "NO_CHANGE" ? 2'b00 :
PORT_B_OPTION_WRITE_MODE == "WRITE_FIRST" ? 2'b01 : 2'b10;
RAM1K20 #(
@ -155,7 +155,7 @@ RAM1K20 #(
.B_DOUT_ARST_N(1'b1),
// Disable ECC for TDP
.ECC_EN(1'b0),
.ECC_EN(1'b0),
.ECC_BYPASS(1'b1),
.BUSY_FB(1'b0)
@ -212,7 +212,7 @@ generate
wire [1:0] A_write_EN;
wire [1:0] B_write_EN;
// write port (A provides MSB)
// write port (A provides MSB)
if (PORT_W_WIDTH == 32) begin
assign B_write_data[3:0] = PORT_W_WR_DATA[3:0];
@ -232,7 +232,7 @@ generate
assign A_write_data[9] = 1'b0;
assign A_write_data[14] = 1'b0;
assign A_write_data[19] = 1'b0;
end else if (PORT_W_WIDTH == 40) begin
assign B_write_data = PORT_W_WR_DATA[19:0];
assign A_write_data = PORT_W_WR_DATA[39:20];
@ -265,7 +265,7 @@ endgenerate
wire [2:0] A_width = (PORT_R_WIDTH == 1) ? 3'b000 :
(PORT_R_WIDTH == 2) ? 3'b001 :
(PORT_R_WIDTH == 4 || PORT_R_WIDTH == 5) ? 3'b010 :
(PORT_R_WIDTH == 8 || PORT_R_WIDTH == 10) ? 3'b011 :
(PORT_R_WIDTH == 8 || PORT_R_WIDTH == 10) ? 3'b011 :
(PORT_R_WIDTH == 16 || PORT_R_WIDTH == 20) ? 3'b100 : 3'b101;
wire [2:0] B_width = (PORT_W_WIDTH == 1) ? 3'b000 :
(PORT_W_WIDTH == 2) ? 3'b001 :
@ -311,7 +311,7 @@ RAM1K20 #(
.B_DOUT_ARST_N(1'b1),
// Disable ECC for SDP
.ECC_EN(1'b0),
.ECC_EN(1'b0),
.ECC_BYPASS(1'b1),
.BUSY_FB(1'b0)
);

2
techlibs/microchip/arith_map.v
View file

@ -48,7 +48,7 @@ module \$__microchip_XOR8_ (A, Y);
XOR8 _TECHMAP_REPLACE_.XOR8 (.A(A[0]), .B(A[1]), .C(A[2]), .D(A[3]), .E(A[4]), .F(A[5]), .G(A[6]), .H(A[7]), .Y(Y));
endmodule
(* techmap_celltype = "$alu" *)

14
techlibs/microchip/cells_sim.v
View file

@ -155,7 +155,7 @@ endmodule
// sequential elements
// MICROCHIP_SYNC_SET_DFF and MICROCHIP_SYNC_RESET_DFF are intermediate cell types to implement the simplification idiom for abc9 flow
// MICROCHIP_SYNC_SET_DFF and MICROCHIP_SYNC_RESET_DFF are intermediate cell types to implement the simplification idiom for abc9 flow
// see: https://yosyshq.readthedocs.io/projects/yosys/en/latest/yosys_internals/extending_yosys/abc_flow.html
(* abc9_flop, lib_whitebox *)
@ -196,7 +196,7 @@ module MICROCHIP_SYNC_RESET_DFF(
always @(posedge CLK) begin
if (En == 1) begin
if (Reset == 0)
if (Reset == 0)
Q <= 0;
else
Q <= D;
@ -258,7 +258,7 @@ module ARI1 (
(* abc9_carry *)
output FCO,
input A, B, C, D,
input A, B, C, D,
output Y, S
);
parameter [19:0] INIT = 20'h0;
@ -271,9 +271,9 @@ module ARI1 (
wire G = INIT[16] ? (INIT[17] ? F1 : F0) : INIT[17];
wire P = INIT[19] ? 1'b1 : (INIT[18] ? Yout : 1'b0);
assign FCO = P ? FCI : G;
specify
//pin to pin path delay
//pin to pin path delay
(A => Y ) = 472;
(B => Y ) = 407;
(C => Y ) = 238;
@ -647,7 +647,7 @@ module RAM1K20 (
input B_DOUT_EN,
input B_DOUT_SRST_N,
input B_DOUT_ARST_N,
input ECC_EN,
input ECC_EN,
input ECC_BYPASS,
output SB_CORRECT,
output DB_DETECT,
@ -684,7 +684,7 @@ module RAM64x12 (
input R_ADDR_EN,
input R_ADDR_SL_N,
input R_ADDR_SD,
input R_ADDR_AL_N,
input R_ADDR_AL_N,
input R_ADDR_AD_N,
input BLK_EN,
output [11:0] R_DATA,

24
techlibs/microchip/microchip_dsp.pmg
View file

@ -1,7 +1,7 @@
// ISC License
//
//
// Copyright (C) 2024 Microchip Technology Inc. and its subsidiaries
//
//
// Permission to use, copy, modify, and/or distribute this software for any
// purpose with or without fee is hereby granted, provided that the above
// copyright notice and this permission notice appear in all copies.
@ -16,12 +16,12 @@
// This file describes the main pattern matcher setup (of three total) that
// forms the `microchip_dsp` pass described in microchip_dsp.cc
// forms the `microchip_dsp` pass described in microchip_dsp.cc
// At a high level, it works as follows:
// ( 1) Starting from a DSP cell. Capture DSP configurations as states
// ( 2) Match for pre-adder
// ( 3) Match for post-adder
// ( 4) Match register 'A', 'B', 'D', 'P'
// ( 4) Match register 'A', 'B', 'D', 'P'
// ( 5) If post-adder and PREG both present, check if PREG feeds into post-adder.
// This indicates an accumulator situation like the ASCII diagram below:
// +--------------------------------+
@ -110,21 +110,21 @@ code bypassA bypassB bypassC bypassD bypassPASUB bypassP
endcode
// (2) Match for pre-adder
//
//
code sigA sigB sigD preAdderStatic moveBtoA
subpattern(preAddMatching);
preAdderStatic = u_preAdderStatic;
moveBtoA = false;
if (preAdderStatic) {
if (port(preAdderStatic, \Y) == sigA)
{
//used for packing
moveBtoA = true;
// sigA should be the input to the multiplier without the preAdd. sigB and sigD should be
//the preAdd inputs. If our "A" input into the multiplier is from the preAdd (not sigA), then
// sigA should be the input to the multiplier without the preAdd. sigB and sigD should be
//the preAdd inputs. If our "A" input into the multiplier is from the preAdd (not sigA), then
// we basically swap it.
sigA = sigB;
}
@ -144,7 +144,7 @@ code postAdderStatic sigP sigC
if (postAdderStatic) {
//sigC will be whichever input to the postAdder that is NOT from the multiplier
// u_postAddAB is the input to the postAdder from the multiplier
// u_postAddAB is the input to the postAdder from the multiplier
sigC = port(postAdderStatic, u_postAddAB == \A ? \B : \A);
sigP = port(postAdderStatic, \Y);
}
@ -269,7 +269,7 @@ code
if (postAdd)
{
if (postAdd->type.in($sub) && postAddAB == \A) {
// if $sub, the multiplier output must match to $sub.B, otherwise no match
// if $sub, the multiplier output must match to $sub.B, otherwise no match
} else {
u_postAddAB = postAddAB;
u_postAdderStatic = postAdd;
@ -286,11 +286,11 @@ endcode
subpattern preAddMatching
arg sigA sigB sigD bypassB bypassD bypassPASUB
code
code
u_preAdderStatic = nullptr;
// Ensure that preAdder not already used
// Assume we can inspect port D to see if its all zeros.
// Assume we can inspect port D to see if its all zeros.
if (!(sigD.empty() || sigD.is_fully_zero())) reject;
if (!bypassB.is_fully_ones()) reject;
if (!bypassD.is_fully_ones()) reject;

6
techlibs/microchip/microchip_dsp_CREG.pmg
View file

@ -1,7 +1,7 @@
// ISC License
//
//
// Copyright (C) 2024 Microchip Technology Inc. and its subsidiaries
//
//
// Permission to use, copy, modify, and/or distribute this software for any
// purpose with or without fee is hereby granted, provided that the above
// copyright notice and this permission notice appear in all copies.
@ -164,5 +164,5 @@ code argQ
argQ = Q;
dffD.replace(argQ, D);
}
endcode

18
techlibs/microchip/microchip_dsp_cascade.pmg
View file

@ -1,7 +1,7 @@
// ISC License
//
//
// Copyright (C) 2024 Microchip Technology Inc. and its subsidiaries
//
//
// Permission to use, copy, modify, and/or distribute this software for any
// purpose with or without fee is hereby granted, provided that the above
// copyright notice and this permission notice appear in all copies.
@ -18,10 +18,10 @@
// This file describes the third of three pattern matcher setups that
// forms the `microchip_dsp` pass described in microchip_dsp.cc
// At a high level, it works as follows:
// (1) Starting from a DSP cell that
// (1) Starting from a DSP cell that
// (a) CDIN_FDBK_SEL is set to default "00"
// (b) doesn't already use the 'PCOUT' port
// (2) Match another DSP cell that
// (2) Match another DSP cell that
// (a) does not have the CREG enabled,
// (b) 'C' port is driven by the 'P' output of the previous DSP cell
// (c) has its 'PCIN' port unused
@ -72,7 +72,7 @@ code
};
endcode
// (1) Starting from a DSP cell that
// (1) Starting from a DSP cell that
// (a) CDIN_FDBK_SEL is set to default "00"
// (b) doesn't already use the 'PCOUT' port
match first
@ -133,7 +133,7 @@ finally
{
dsp_pcin->setPort(\ARSHFT17, State::S1);
}
log_debug("PCOUT -> PCIN cascade for %s -> %s\n", dsp, dsp_pcin);
@ -154,7 +154,7 @@ subpattern tail
arg first
arg next
// (2) Match another DSP cell that
// (2) Match another DSP cell that
// (a) does not have the CREG enabled,
// (b) 'C' port is driven by the 'P' output of the previous DSP cell
// (c) has its 'PCIN' port unused
@ -213,7 +213,7 @@ code
chain.emplace_back(next, shift);
visited.insert(next);
SigSpec sigC = unextend(port(next, \C));
// Make sure driverDSP.P === DSP.C
@ -231,6 +231,6 @@ finally
visited.erase(next);
chain.pop_back();
}
endcode

10
techlibs/microchip/polarfire_dsp_map.v
View file

@ -27,9 +27,9 @@ module \$__MUL18X18 (input [17:0] A, input [17:0] B, output [35:0] Y);
// For pin descriptions, see Section 9 of PolarFire FPGA Macro Library Guide:
// https://coredocs.s3.amazonaws.com/Libero/2021_2/Tool/pf_mlg.pdf
MACC_PA _TECHMAP_REPLACE_ (
.DOTP(1'b0),
.SIMD(1'b0),
.OVFL_CARRYOUT_SEL(1'b0),
.DOTP(1'b0),
.SIMD(1'b0),
.OVFL_CARRYOUT_SEL(1'b0),
.AL_N(1'b1),
.A(A),
@ -47,7 +47,7 @@ module \$__MUL18X18 (input [17:0] A, input [17:0] B, output [35:0] Y);
.D_ARST_N(1'b1),
.D_SRST_N(1'b1),
.D_EN(1'b1),
.CARRYIN(1'b0),
.C(48'b0),
.C_BYPASS(1'b1),
@ -55,7 +55,7 @@ module \$__MUL18X18 (input [17:0] A, input [17:0] B, output [35:0] Y);
.C_SRST_N(1'b1),
.C_EN(1'b1),
.P(P_48),
.P_BYPASS(1'b1),

12
techlibs/microchip/uSRAM.txt
View file

@ -1,11 +1,11 @@
# ISC License
#
#
# Copyright (C) 2024 Microchip Technology Inc. and its subsidiaries
#
#
# Permission to use, copy, modify, and/or distribute this software for any
# purpose with or without fee is hereby granted, provided that the above
# copyright notice and this permission notice appear in all copies.
#
#
# THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
# WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
# MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
@ -30,10 +30,10 @@ ram block $__uSRAM_AR_ {
port sw "W" {
clock posedge;
# collision not supported, but write takes precedence and read data is invalid while writing to
# collision not supported, but write takes precedence and read data is invalid while writing to
# the same address
wrtrans all new;
optional;
}
port ar "R" {
@ -57,7 +57,7 @@ widths 12 per_port;
# collision not supported
wrtrans all new;
optional;
}
port sr "R" {

4
techlibs/microchip/uSRAM_map.v
View file

@ -48,7 +48,7 @@ RAM64x12 #(
.R_ADDR_EN(1'b0),
.R_ADDR_SL_N(1'b1),
.R_ADDR_SD(1'b0),
.R_ADDR_AL_N(1'b1),
.R_ADDR_AL_N(1'b1),
.R_ADDR_AD_N(1'b0),
.BLK_EN(PORT_R_USED ? 1'b1 : 1'b0),
.R_DATA(PORT_R_RD_DATA),
@ -103,7 +103,7 @@ RAM64x12 #(
.R_ADDR_EN(PORT_R_RD_EN),
.R_ADDR_SL_N(1'b1),
.R_ADDR_SD(1'b0),
.R_ADDR_AL_N(1'b1),
.R_ADDR_AL_N(1'b1),
.R_ADDR_AD_N(1'b0),
.BLK_EN(PORT_R_USED ? 1'b1 : 1'b0),
.R_DATA(PORT_R_RD_DATA),