mirrors/yosys
3
0
Fork 0
mirror of https://github.com/YosysHQ/yosys synced 2026-06-29 12:08:51 +00:00
Code Activity

Remove trailing whitespaces

Browse source
This commit is contained in:
Miodrag Milanovic 2026-06-23 07:24:59 +02:00
parent 48a3dcc02a
commit a689342207
317 changed files with 3136 additions and 3136 deletions
Download patch file Download diff file Expand all files Collapse all files

16
techlibs/anlogic/anlogic_fixcarry.cc
View file

@ -48,8 +48,8 @@ static void fix_carry_chain(Module *module)
SigSpec o = cell->getPort(ID(o));
if (GetSize(o) == 2) {
SigBit bit_o = o[0];
ci_bits.insert(bit_ci);
mapping_bits[bit_ci] = bit_o;
ci_bits.insert(bit_ci);
mapping_bits[bit_ci] = bit_o;
}
}
}
@ -64,8 +64,8 @@ static void fix_carry_chain(Module *module)
SigBit bit_i1 = get_bit_or_zero(cell->getPort(ID(b)));
SigBit canonical_bit = sigmap(bit_ci);
if (!ci_bits.count(canonical_bit))
continue;
if (bit_i0 == State::S0 && bit_i1== State::S0)
continue;
if (bit_i0 == State::S0 && bit_i1== State::S0)
continue;
adders_to_fix_cells.push_back(cell);
@ -90,10 +90,10 @@ static void fix_carry_chain(Module *module)
c->setPort(ID(b), State::S0);
c->setPort(ID(c), State::S0);
c->setPort(ID(o), bits);
cell->setPort(ID(c), new_bit);
}
}
struct AnlogicCarryFixPass : public Pass {
@ -110,7 +110,7 @@ struct AnlogicCarryFixPass : public Pass {
void execute(std::vector<std::string> args, RTLIL::Design *design) override
{
log_header(design, "Executing anlogic_fixcarry pass (fix invalid carry chain).\n");
size_t argidx;
for (argidx = 1; argidx < args.size(); argidx++)
{
@ -123,7 +123,7 @@ struct AnlogicCarryFixPass : public Pass {
if (module == nullptr)
log_cmd_error("No top module found.\n");
fix_carry_chain(module);
fix_carry_chain(module);
}
} AnlogicCarryFixPass;

4
techlibs/anlogic/arith_map.v
View file

@ -36,7 +36,7 @@ module _80_anlogic_alu (A, B, CI, BI, X, Y, CO);
input CI, BI;
(* force_downto *)
output [Y_WIDTH-1:0] CO;
wire CIx;
(* force_downto *)
wire [Y_WIDTH-1:0] COx;
@ -85,7 +85,7 @@ module _80_anlogic_alu (A, B, CI, BI, X, Y, CO);
.c(COx[i]),
.o({cout, CO[i]})
);
end: slice
end: slice
endgenerate
/* End implementation */

10
techlibs/anlogic/cells_sim.v
View file

@ -82,7 +82,7 @@ module AL_MAP_LUT1 (
parameter [1:0] INIT = 2'h0;
parameter EQN = "(A)";
assign o = a ? INIT[1] : INIT[0];
assign o = a ? INIT[1] : INIT[0];
endmodule
module AL_MAP_LUT2 (
@ -94,7 +94,7 @@ module AL_MAP_LUT2 (
parameter EQN = "(A)";
wire [1:0] s1 = b ? INIT[ 3:2] : INIT[1:0];
assign o = a ? s1[1] : s1[0];
assign o = a ? s1[1] : s1[0];
endmodule
module AL_MAP_LUT3 (
@ -108,7 +108,7 @@ module AL_MAP_LUT3 (
wire [3:0] s2 = c ? INIT[ 7:4] : INIT[3:0];
wire [1:0] s1 = b ? s2[ 3:2] : s2[1:0];
assign o = a ? s1[1] : s1[0];
assign o = a ? s1[1] : s1[0];
endmodule
module AL_MAP_LUT4 (
@ -124,7 +124,7 @@ module AL_MAP_LUT4 (
wire [7:0] s3 = d ? INIT[15:8] : INIT[7:0];
wire [3:0] s2 = c ? s3[ 7:4] : s3[3:0];
wire [1:0] s1 = b ? s2[ 3:2] : s2[1:0];
assign o = a ? s1[1] : s1[0];
assign o = a ? s1[1] : s1[0];
endmodule
module AL_MAP_LUT5 (
@ -186,6 +186,6 @@ module AL_MAP_ADDER (
"A_LE_B_CARRY": assign o = { a, 1'b0 };
default: assign o = a + b + c;
endcase
endgenerate
endgenerate
endmodule

24
techlibs/anlogic/eagle_bb.v
View file

@ -44,7 +44,7 @@ endmodule
(* blackbox *)
module EG_LOGIC_MBOOT(
input rebootn,
input [7:0] dynamic_addr
input [7:0] dynamic_addr
);
parameter ADDR_SOURCE_SEL = "STATIC";
parameter STATIC_ADDR = 8'b00000000;
@ -242,7 +242,7 @@ module EG_LOGIC_MULT(
input rstan,
input rstbn,
input rstpdn
);
);
parameter INPUT_WIDTH_A = 18;
parameter INPUT_WIDTH_B = 18;
parameter OUTPUT_WIDTH = 36;
@ -561,7 +561,7 @@ module EG_PHY_FIFO(
parameter [13:0] F = 14'b01111111110000;
parameter [13:0] AEP1 = 14'b00000001110000;
parameter [13:0] AFM1 = 14'b01111110000000;
parameter [13:0] FM1 = 14'b01111111100000;
parameter [13:0] FM1 = 14'b01111111100000;
parameter [4:0] E = 5'b00000;
parameter [5:0] EP1 = 6'b010000;
parameter GSR = "ENABLE";
@ -604,8 +604,8 @@ module EG_PHY_MULT18(
input rstbn,
input rstpdn,
input sourcea,
input sourceb
);
input sourceb
);
parameter INPUTREGA = "ENABLE";
parameter INPUTREGB = "ENABLE";
parameter OUTPUTREG = "ENABLE";
@ -628,7 +628,7 @@ endmodule
module EG_PHY_GCLK(
input clki,
output clko
);
);
endmodule
(* blackbox *)
@ -647,7 +647,7 @@ module EG_PHY_CLKDIV(
input clki,
input rst,
input rls
);
);
parameter GSR = "DISABLE";
parameter DIV = 2;
endmodule
@ -677,7 +677,7 @@ module EG_PHY_CONFIG(
input dna_shift_en,
input mboot_rebootn,
input [7:0] mboot_dynamic_addr
);
);
parameter MBOOT_AUTO_SEL = "DISABLE";
parameter ADDR_SOURCE_SEL = "STATIC";
parameter STATIC_ADDR = 8'b0;
@ -694,7 +694,7 @@ endmodule
module EG_PHY_OSC(
input osc_dis,
output osc_clk
);
);
parameter STDBY = "DISABLE";
endmodule
@ -919,7 +919,7 @@ module EG_PHY_PLL(
parameter CLKC3_DIV2_ENABLE = "DISABLE";
parameter CLKC4_DIV2_ENABLE = "DISABLE";
parameter FEEDBK_MODE = "NORMAL";
parameter FEEDBK_PATH = "VCO_PHASE_0";
parameter FEEDBK_PATH = "VCO_PHASE_0";
parameter STDBY_ENABLE = "ENABLE";
parameter CLKC0_FPHASE = 0;
parameter CLKC1_FPHASE = 0;
@ -992,7 +992,7 @@ module EG_LOGIC_BRAM(
parameter DATA_DEPTH_B = 2 ** ADDR_WIDTH_B;
parameter BYTE_ENABLE = 0;
parameter BYTE_A = BYTE_ENABLE == 0 ? 1 : DATA_WIDTH_A / BYTE_ENABLE;
parameter BYTE_B = BYTE_ENABLE == 0 ? 1 : DATA_WIDTH_B / BYTE_ENABLE;
parameter BYTE_B = BYTE_ENABLE == 0 ? 1 : DATA_WIDTH_B / BYTE_ENABLE;
parameter MODE = "DP";
parameter REGMODE_A = "NOREG";
parameter REGMODE_B = "NOREG";
@ -1005,7 +1005,7 @@ module EG_LOGIC_BRAM(
parameter INIT_FILE = "NONE";
parameter FILL_ALL = "NONE";
parameter IMPLEMENT = "9K";
endmodule
endmodule
(* blackbox *)
module EG_PHY_ADC(