mirrors/yosys
3
0
Fork 0
mirror of https://github.com/YosysHQ/yosys synced 2026-06-29 03:58:50 +00:00
Code Activity

Remove trailing whitespaces

Browse source
This commit is contained in:
Miodrag Milanovic 2026-06-23 07:24:59 +02:00
parent 48a3dcc02a
commit a689342207
317 changed files with 3136 additions and 3136 deletions
Download patch file Download diff file Expand all files Collapse all files

4
techlibs/analogdevices/cells_sim.v
View file

@ -958,7 +958,7 @@ module RAMD64X1 (
(DPRA2 => DPO) = 147;
(DPRA3 => DPO) = 139;
(DPRA4 => DPO) = 131;
(DPRA5 => DPO) = 64;
(DPRA5 => DPO) = 64;
(posedge WCLK => (SPO : D)) = 761;
(posedge WCLK => (DPO : D)) = 733;
endspecify
@ -984,7 +984,7 @@ module RAMD64X1 (
(DPRA2 => DPO) = 513;
(DPRA3 => DPO) = 505;
(DPRA4 => DPO) = 496;
(DPRA5 => DPO) = 199;
(DPRA5 => DPO) = 199;
(posedge WCLK => (SPO : D)) = 1798;
(posedge WCLK => (DPO : D)) = 1807;
endspecify