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Remove trailing whitespaces

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This commit is contained in:
Miodrag Milanovic 2026-06-23 07:24:59 +02:00
parent 48a3dcc02a
commit a689342207
317 changed files with 3136 additions and 3136 deletions
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4
techlibs/analogdevices/cells_sim.v
View file

@ -958,7 +958,7 @@ module RAMD64X1 (
(DPRA2 => DPO) = 147;
(DPRA3 => DPO) = 139;
(DPRA4 => DPO) = 131;
(DPRA5 => DPO) = 64;
(DPRA5 => DPO) = 64;
(posedge WCLK => (SPO : D)) = 761;
(posedge WCLK => (DPO : D)) = 733;
endspecify
@ -984,7 +984,7 @@ module RAMD64X1 (
(DPRA2 => DPO) = 513;
(DPRA3 => DPO) = 505;
(DPRA4 => DPO) = 496;
(DPRA5 => DPO) = 199;
(DPRA5 => DPO) = 199;
(posedge WCLK => (SPO : D)) = 1798;
(posedge WCLK => (DPO : D)) = 1807;
endspecify

16
techlibs/anlogic/anlogic_fixcarry.cc
View file

@ -48,8 +48,8 @@ static void fix_carry_chain(Module *module)
SigSpec o = cell->getPort(ID(o));
if (GetSize(o) == 2) {
SigBit bit_o = o[0];
ci_bits.insert(bit_ci);
mapping_bits[bit_ci] = bit_o;
ci_bits.insert(bit_ci);
mapping_bits[bit_ci] = bit_o;
}
}
}
@ -64,8 +64,8 @@ static void fix_carry_chain(Module *module)
SigBit bit_i1 = get_bit_or_zero(cell->getPort(ID(b)));
SigBit canonical_bit = sigmap(bit_ci);
if (!ci_bits.count(canonical_bit))
continue;
if (bit_i0 == State::S0 && bit_i1== State::S0)
continue;
if (bit_i0 == State::S0 && bit_i1== State::S0)
continue;
adders_to_fix_cells.push_back(cell);
@ -90,10 +90,10 @@ static void fix_carry_chain(Module *module)
c->setPort(ID(b), State::S0);
c->setPort(ID(c), State::S0);
c->setPort(ID(o), bits);
cell->setPort(ID(c), new_bit);
}
}
struct AnlogicCarryFixPass : public Pass {
@ -110,7 +110,7 @@ struct AnlogicCarryFixPass : public Pass {
void execute(std::vector<std::string> args, RTLIL::Design *design) override
{
log_header(design, "Executing anlogic_fixcarry pass (fix invalid carry chain).\n");
size_t argidx;
for (argidx = 1; argidx < args.size(); argidx++)
{
@ -123,7 +123,7 @@ struct AnlogicCarryFixPass : public Pass {
if (module == nullptr)
log_cmd_error("No top module found.\n");
fix_carry_chain(module);
fix_carry_chain(module);
}
} AnlogicCarryFixPass;

4
techlibs/anlogic/arith_map.v
View file

@ -36,7 +36,7 @@ module _80_anlogic_alu (A, B, CI, BI, X, Y, CO);
input CI, BI;
(* force_downto *)
output [Y_WIDTH-1:0] CO;
wire CIx;
(* force_downto *)
wire [Y_WIDTH-1:0] COx;
@ -85,7 +85,7 @@ module _80_anlogic_alu (A, B, CI, BI, X, Y, CO);
.c(COx[i]),
.o({cout, CO[i]})
);
end: slice
end: slice
endgenerate
/* End implementation */

10
techlibs/anlogic/cells_sim.v
View file

@ -82,7 +82,7 @@ module AL_MAP_LUT1 (
parameter [1:0] INIT = 2'h0;
parameter EQN = "(A)";
assign o = a ? INIT[1] : INIT[0];
assign o = a ? INIT[1] : INIT[0];
endmodule
module AL_MAP_LUT2 (
@ -94,7 +94,7 @@ module AL_MAP_LUT2 (
parameter EQN = "(A)";
wire [1:0] s1 = b ? INIT[ 3:2] : INIT[1:0];
assign o = a ? s1[1] : s1[0];
assign o = a ? s1[1] : s1[0];
endmodule
module AL_MAP_LUT3 (
@ -108,7 +108,7 @@ module AL_MAP_LUT3 (
wire [3:0] s2 = c ? INIT[ 7:4] : INIT[3:0];
wire [1:0] s1 = b ? s2[ 3:2] : s2[1:0];
assign o = a ? s1[1] : s1[0];
assign o = a ? s1[1] : s1[0];
endmodule
module AL_MAP_LUT4 (
@ -124,7 +124,7 @@ module AL_MAP_LUT4 (
wire [7:0] s3 = d ? INIT[15:8] : INIT[7:0];
wire [3:0] s2 = c ? s3[ 7:4] : s3[3:0];
wire [1:0] s1 = b ? s2[ 3:2] : s2[1:0];
assign o = a ? s1[1] : s1[0];
assign o = a ? s1[1] : s1[0];
endmodule
module AL_MAP_LUT5 (
@ -186,6 +186,6 @@ module AL_MAP_ADDER (
"A_LE_B_CARRY": assign o = { a, 1'b0 };
default: assign o = a + b + c;
endcase
endgenerate
endgenerate
endmodule

24
techlibs/anlogic/eagle_bb.v
View file

@ -44,7 +44,7 @@ endmodule
(* blackbox *)
module EG_LOGIC_MBOOT(
input rebootn,
input [7:0] dynamic_addr
input [7:0] dynamic_addr
);
parameter ADDR_SOURCE_SEL = "STATIC";
parameter STATIC_ADDR = 8'b00000000;
@ -242,7 +242,7 @@ module EG_LOGIC_MULT(
input rstan,
input rstbn,
input rstpdn
);
);
parameter INPUT_WIDTH_A = 18;
parameter INPUT_WIDTH_B = 18;
parameter OUTPUT_WIDTH = 36;
@ -561,7 +561,7 @@ module EG_PHY_FIFO(
parameter [13:0] F = 14'b01111111110000;
parameter [13:0] AEP1 = 14'b00000001110000;
parameter [13:0] AFM1 = 14'b01111110000000;
parameter [13:0] FM1 = 14'b01111111100000;
parameter [13:0] FM1 = 14'b01111111100000;
parameter [4:0] E = 5'b00000;
parameter [5:0] EP1 = 6'b010000;
parameter GSR = "ENABLE";
@ -604,8 +604,8 @@ module EG_PHY_MULT18(
input rstbn,
input rstpdn,
input sourcea,
input sourceb
);
input sourceb
);
parameter INPUTREGA = "ENABLE";
parameter INPUTREGB = "ENABLE";
parameter OUTPUTREG = "ENABLE";
@ -628,7 +628,7 @@ endmodule
module EG_PHY_GCLK(
input clki,
output clko
);
);
endmodule
(* blackbox *)
@ -647,7 +647,7 @@ module EG_PHY_CLKDIV(
input clki,
input rst,
input rls
);
);
parameter GSR = "DISABLE";
parameter DIV = 2;
endmodule
@ -677,7 +677,7 @@ module EG_PHY_CONFIG(
input dna_shift_en,
input mboot_rebootn,
input [7:0] mboot_dynamic_addr
);
);
parameter MBOOT_AUTO_SEL = "DISABLE";
parameter ADDR_SOURCE_SEL = "STATIC";
parameter STATIC_ADDR = 8'b0;
@ -694,7 +694,7 @@ endmodule
module EG_PHY_OSC(
input osc_dis,
output osc_clk
);
);
parameter STDBY = "DISABLE";
endmodule
@ -919,7 +919,7 @@ module EG_PHY_PLL(
parameter CLKC3_DIV2_ENABLE = "DISABLE";
parameter CLKC4_DIV2_ENABLE = "DISABLE";
parameter FEEDBK_MODE = "NORMAL";
parameter FEEDBK_PATH = "VCO_PHASE_0";
parameter FEEDBK_PATH = "VCO_PHASE_0";
parameter STDBY_ENABLE = "ENABLE";
parameter CLKC0_FPHASE = 0;
parameter CLKC1_FPHASE = 0;
@ -992,7 +992,7 @@ module EG_LOGIC_BRAM(
parameter DATA_DEPTH_B = 2 ** ADDR_WIDTH_B;
parameter BYTE_ENABLE = 0;
parameter BYTE_A = BYTE_ENABLE == 0 ? 1 : DATA_WIDTH_A / BYTE_ENABLE;
parameter BYTE_B = BYTE_ENABLE == 0 ? 1 : DATA_WIDTH_B / BYTE_ENABLE;
parameter BYTE_B = BYTE_ENABLE == 0 ? 1 : DATA_WIDTH_B / BYTE_ENABLE;
parameter MODE = "DP";
parameter REGMODE_A = "NOREG";
parameter REGMODE_B = "NOREG";
@ -1005,7 +1005,7 @@ module EG_LOGIC_BRAM(
parameter INIT_FILE = "NONE";
parameter FILL_ALL = "NONE";
parameter IMPLEMENT = "9K";
endmodule
endmodule
(* blackbox *)
module EG_PHY_ADC(

4
techlibs/common/mul2dsp.v
View file

@ -20,8 +20,8 @@
* ---
*
* Tech-mapping rules for decomposing arbitrarily-sized $mul cells
* into an equivalent collection of smaller `DSP_NAME cells (with the
* same interface as $mul) no larger than `DSP_[AB]_MAXWIDTH, attached
* into an equivalent collection of smaller `DSP_NAME cells (with the
* same interface as $mul) no larger than `DSP_[AB]_MAXWIDTH, attached
* to $shl and $add cells.
*
*/

16
techlibs/common/simlib.v
View file

@ -476,7 +476,7 @@ endmodule
//- $sshl (A, B, Y)
//* group binary
//-
//- An arithmatic shift-left operation.
//- An arithmatic shift-left operation.
//- This corresponds to the Verilog '<<<' operator.
//-
module \$sshl (A, B, Y);
@ -720,7 +720,7 @@ endmodule
//- $lt (A, B, Y)
//* group binary
//-
//- A less-than comparison between inputs 'A' and 'B'.
//- A less-than comparison between inputs 'A' and 'B'.
//- This corresponds to the Verilog '<' operator.
//-
module \$lt (A, B, Y);
@ -752,7 +752,7 @@ endmodule
//- $le (A, B, Y)
//* group binary
//-
//- A less-than-or-equal-to comparison between inputs 'A' and 'B'.
//- A less-than-or-equal-to comparison between inputs 'A' and 'B'.
//- This corresponds to the Verilog '<=' operator.
//-
module \$le (A, B, Y);
@ -784,7 +784,7 @@ endmodule
//- $eq (A, B, Y)
//* group binary
//-
//- An equality comparison between inputs 'A' and 'B'.
//- An equality comparison between inputs 'A' and 'B'.
//- This corresponds to the Verilog '==' operator.
//-
module \$eq (A, B, Y);
@ -816,7 +816,7 @@ endmodule
//- $ne (A, B, Y)
//* group binary
//-
//- An inequality comparison between inputs 'A' and 'B'.
//- An inequality comparison between inputs 'A' and 'B'.
//- This corresponds to the Verilog '!=' operator.
//-
module \$ne (A, B, Y);
@ -944,7 +944,7 @@ endmodule
//- $gt (A, B, Y)
//* group binary
//-
//- A greater-than comparison between inputs 'A' and 'B'.
//- A greater-than comparison between inputs 'A' and 'B'.
//- This corresponds to the Verilog '>' operator.
//-
module \$gt (A, B, Y);
@ -1477,7 +1477,7 @@ endmodule
//- $pow (A, B, Y)
//* group binary
//-
//- Exponentiation of an input (Y = A ** B).
//- Exponentiation of an input (Y = A ** B).
//- This corresponds to the Verilog '**' operator.
//-
`ifndef SIMLIB_NOPOW
@ -1809,7 +1809,7 @@ endmodule
//-
//- $tribuf (A, EN, Y)
//-
//- A tri-state buffer.
//- A tri-state buffer.
//- This buffer conditionally drives the output with the value of the input
//- based on the enable signal.
//-

6
techlibs/efinix/arith_map.v
View file

@ -36,7 +36,7 @@ module _80_efinix_alu (A, B, CI, BI, X, Y, CO);
input CI, BI;
(* force_downto *)
output [Y_WIDTH-1:0] CO;
wire CIx;
(* force_downto *)
wire [Y_WIDTH-1:0] COx;
@ -73,14 +73,14 @@ module _80_efinix_alu (A, B, CI, BI, X, Y, CO);
.O(Y[i]),
.CO(COx[i])
);
EFX_ADD #(.I0_POLARITY(1'b1),.I1_POLARITY(1'b1))
EFX_ADD #(.I0_POLARITY(1'b1),.I1_POLARITY(1'b1))
adder_cout (
.I0(1'b0),
.I1(1'b0),
.CI(COx[i]),
.O(CO[i])
);
end: slice
end: slice
endgenerate
/* End implementation */

4
techlibs/efinix/brams_map.v
View file

@ -33,14 +33,14 @@ module $__EFINIX_5K_ (...);
PORT_W_WIDTH == 10 ? 9 :
8;
localparam READ_WIDTH =
localparam READ_WIDTH =
PORT_R_WIDTH == 1 ? 1 :
PORT_R_WIDTH == 2 ? 2 :
PORT_R_WIDTH == 5 ? (IS_5BIT ? 5 : 4) :
PORT_R_WIDTH == 10 ? (IS_5BIT ? 10 : 8) :
(IS_5BIT ? 20 : 16);
localparam WRITE_WIDTH =
localparam WRITE_WIDTH =
PORT_W_WIDTH == 1 ? 1 :
PORT_W_WIDTH == 2 ? 2 :
PORT_W_WIDTH == 5 ? (IS_5BIT ? 5 : 4) :

28
techlibs/efinix/cells_sim.v
View file

@ -1,5 +1,5 @@
module EFX_LUT4(
output O,
output O,
input I0,
input I1,
input I2,
@ -10,7 +10,7 @@ module EFX_LUT4(
wire [7:0] s3 = I3 ? LUTMASK[15:8] : LUTMASK[7:0];
wire [3:0] s2 = I2 ? s3[ 7:4] : s3[3:0];
wire [1:0] s1 = I1 ? s2[ 3:2] : s2[1:0];
assign O = I0 ? s1[1] : s1[0];
assign O = I0 ? s1[1] : s1[0];
endmodule
module EFX_ADD(
@ -64,9 +64,9 @@ module EFX_FF(
initial Q = 1'b0;
generate
if (SR_SYNC == 1)
if (SR_SYNC == 1)
begin
if (SR_SYNC_PRIORITY == 1)
if (SR_SYNC_PRIORITY == 1)
begin
always @(posedge clk)
if (sr)
@ -93,7 +93,7 @@ module EFX_FF(
Q <= SR_VALUE;
else if (ce)
Q <= d;
end
endgenerate
endmodule
@ -108,16 +108,16 @@ module EFX_GBUFCE(
wire ce;
assign ce = CE_POLARITY ? CE : ~CE;
assign O = I & ce;
endmodule
module EFX_RAM_5K
# (
parameter READ_WIDTH = 20,
parameter WRITE_WIDTH = 20,
localparam READ_ADDR_WIDTH =
localparam READ_ADDR_WIDTH =
(READ_WIDTH == 16) ? 8 : // 256x16
(READ_WIDTH == 8) ? 9 : // 512x8
(READ_WIDTH == 4) ? 10 : // 1024x4
@ -126,8 +126,8 @@ module EFX_RAM_5K
(READ_WIDTH == 20) ? 8 : // 256x20
(READ_WIDTH == 10) ? 9 : // 512x10
(READ_WIDTH == 5) ? 10 : -1, // 1024x5
localparam WRITE_ADDR_WIDTH =
localparam WRITE_ADDR_WIDTH =
(WRITE_WIDTH == 16) ? 8 : // 256x16
(WRITE_WIDTH == 8) ? 9 : // 512x8
(WRITE_WIDTH == 4) ? 10 : // 1024x4
@ -140,13 +140,13 @@ module EFX_RAM_5K
(
input [WRITE_WIDTH-1:0] WDATA,
input [WRITE_ADDR_WIDTH-1:0] WADDR,
input WE,
input WE,
(* clkbuf_sink *)
input WCLK,
input WCLKE,
output [READ_WIDTH-1:0] RDATA,
input WCLKE,
output [READ_WIDTH-1:0] RDATA,
input [READ_ADDR_WIDTH-1:0] RADDR,
input RE,
input RE,
(* clkbuf_sink *)
input RCLK
);

14
techlibs/efinix/efinix_fixcarry.cc
View file

@ -45,12 +45,12 @@ static void fix_carry_chain(Module *module)
if (bit_i0 == State::S0 && bit_i1== State::S0) {
SigBit bit_ci = get_bit_or_zero(cell->getPort(ID::CI));
SigBit bit_o = sigmap(cell->getPort(ID::O));
ci_bits.insert(bit_ci);
ci_bits.insert(bit_ci);
mapping_bits[bit_ci] = bit_o;
}
}
}
vector<Cell*> adders_to_fix_cells;
for (auto cell : module->cells())
{
@ -60,8 +60,8 @@ static void fix_carry_chain(Module *module)
SigBit bit_i1 = get_bit_or_zero(cell->getPort(ID(I1)));
SigBit canonical_bit = sigmap(bit_ci);
if (!ci_bits.count(canonical_bit))
continue;
if (bit_i0 == State::S0 && bit_i1== State::S0)
continue;
if (bit_i0 == State::S0 && bit_i1== State::S0)
continue;
adders_to_fix_cells.push_back(cell);
@ -83,7 +83,7 @@ static void fix_carry_chain(Module *module)
c->setPort(ID(I1), State::S1);
c->setPort(ID::CI, State::S0);
c->setPort(ID::CO, new_bit);
cell->setPort(ID::CI, new_bit);
}
}
@ -102,7 +102,7 @@ struct EfinixCarryFixPass : public Pass {
void execute(std::vector<std::string> args, RTLIL::Design *design) override
{
log_header(design, "Executing EFINIX_FIXCARRY pass (fix invalid carry chain).\n");
size_t argidx;
for (argidx = 1; argidx < args.size(); argidx++)
{
@ -115,7 +115,7 @@ struct EfinixCarryFixPass : public Pass {
if (module == nullptr)
log_cmd_error("No top module found.\n");
fix_carry_chain(module);
fix_carry_chain(module);
}
} EfinixCarryFixPass;

26
techlibs/fabulous/prims.v
View file

@ -108,7 +108,7 @@ module FABULOUS_LC #(
output Q
);
wire f_wire;
//LUT #(.K(K), .INIT(INIT)) lut_i(.I(I), .Q(f_wire));
generate
if (K == 1) begin
@ -124,7 +124,7 @@ module FABULOUS_LC #(
LUT4 #(.INIT(INIT)) lut4 (.O(f_wire), .I0(I[0]), .I1(I[1]), .I2(I[2]), .I3(I[3]));
end
endgenerate
LUTFF dff_i(.CLK(CLK), .D(f_wire), .Q(Q));
assign O = f_wire;
@ -255,15 +255,15 @@ module MULADD (A7, A6, A5, A4, A3, A2, A1, A0, B7, B6, B5, B4, B3, B2, B1, B0, C
// GLOBAL all primitive pins that are connected to the switch matrix have to go before the GLOBAL label
wire [7:0] A; // port A read data
wire [7:0] B; // port B read data
wire [19:0] C; // port B read data
wire [7:0] A; // port A read data
wire [7:0] B; // port B read data
wire [19:0] C; // port B read data
reg [7:0] A_q; // port A read data register
reg [7:0] B_q; // port B read data register
reg [19:0] C_q; // port B read data register
wire [7:0] OPA; // port A
wire [7:0] OPB; // port B
wire [19:0] OPC; // port B
wire [7:0] OPA; // port A
wire [7:0] OPB; // port B
wire [19:0] OPC; // port B
reg [19:0] ACC_data ; // accumulator register
wire [19:0] sum;// port B read data register
wire [19:0] sum_in;// port B read data register
@ -337,7 +337,7 @@ module RegFile_32x4 (D0, D1, D2, D3, W_ADR0, W_ADR1, W_ADR2, W_ADR3, W_ADR4, W_e
input W_ADR3;
input W_ADR4;
input W_en;
output AD0;// Register File read port A
output AD1;
output AD2;
@ -359,9 +359,9 @@ module RegFile_32x4 (D0, D1, D2, D3, W_ADR0, W_ADR1, W_ADR2, W_ADR3, W_ADR4, W_e
input B_ADR4;
input CLK;// EXTERNAL // SHARED_PORT // ## the EXTERNAL keyword will send this sisgnal all the way to top and the //SHARED Allows multiple BELs using the same port (e.g. for exporting a clock to the top)
// GLOBAL all primitive pins that are connected to the switch matrix have to go before the GLOBAL label
//type memtype is array (31 downto 0) of std_logic_vector(3 downto 0); // 32 entries of 4 bit
//signal mem : memtype := (others => (others => '0'));
@ -377,7 +377,7 @@ module RegFile_32x4 (D0, D1, D2, D3, W_ADR0, W_ADR1, W_ADR2, W_ADR3, W_ADR4, W_e
reg [3:0] AD_q; // port A read data register
reg [3:0] BD_q; // port B read data register
integer i;
assign W_ADR = {W_ADR4,W_ADR3,W_ADR2,W_ADR1,W_ADR0};
@ -385,7 +385,7 @@ module RegFile_32x4 (D0, D1, D2, D3, W_ADR0, W_ADR1, W_ADR2, W_ADR3, W_ADR4, W_e
assign B_ADR = {B_ADR4,B_ADR3,B_ADR2,B_ADR1,B_ADR0};
assign D = {D3,D2,D1,D0};
initial begin
for (i=0; i<32; i=i+1) begin
mem[i] = 4'b0000;

2
techlibs/fix_mod.py
View file

@ -23,7 +23,7 @@ def main():
in_mod = True
elif in_mod:
decl += line
if in_mod and decl.rstrip()[-1] == ';':
in_mod = False
modules[mod] = decl

2
techlibs/gatemate/gatemate_foldinv.cc
View file

@ -211,7 +211,7 @@ struct GatemateFoldInvPass : public Pass {
for (Module *module : design->selected_modules()) {
FoldInvWorker worker(module);
worker();
}
}
}
} GatemateFoldInvPass;

24
techlibs/gowin/cells_sim.v
View file

@ -25,7 +25,7 @@ module LUT3(output F, input I0, I1, I2);
(I0 => F) = (1054, 1486);
(I1 => F) = (867, 1184);
(I2 => F) = (555, 902);
endspecify
endspecify
wire [ 3: 0] s2 = I2 ? INIT[ 7: 4] : INIT[ 3: 0];
wire [ 1: 0] s1 = I1 ? s2[ 3: 2] : s2[ 1: 0];
assign F = I0 ? s1[1] : s1[0];
@ -39,7 +39,7 @@ module LUT4(output F, input I0, I1, I2, I3);
(I1 => F) = (1053, 1583);
(I2 => F) = (867, 1184);
(I3 => F) = (555, 902);
endspecify
endspecify
wire [ 7: 0] s3 = I3 ? INIT[15: 8] : INIT[ 7: 0];
wire [ 3: 0] s2 = I2 ? s3[ 7: 4] : s3[ 3: 0];
wire [ 1: 0] s1 = I1 ? s2[ 3: 2] : s2[ 1: 0];
@ -54,7 +54,7 @@ module __APICULA_LUT5(output F, input I0, I1, I2, I3, M0);
(I2 => F) = (995, 1371);
(I3 => F) = (808, 1116);
(M0 => F) = (486, 680);
endspecify
endspecify
endmodule
(* abc9_lut=4 *)
@ -66,7 +66,7 @@ module __APICULA_LUT6(output F, input I0, I1, I2, I3, M0, M1);
(I3 => F) = (808 + 136, 1116 + 255);
(M0 => F) = (486 + 136, 680 + 255);
(M1 => F) = (478, 723);
endspecify
endspecify
endmodule
(* abc9_lut=8 *)
@ -79,7 +79,7 @@ module __APICULA_LUT7(output F, input I0, I1, I2, I3, M0, M1, M2);
(M0 => F) = (486 + 136 + 136, 680 + 255 + 255);
(M1 => F) = (478 + 136, 723 + 255);
(M2 => F) = (478, 723);
endspecify
endspecify
endmodule
(* abc9_lut=16 *)
@ -93,7 +93,7 @@ module __APICULA_LUT8(output F, input I0, I1, I2, I3, M0, M1, M2, M3);
(M1 => F) = (478 + 136 + 136, 723 + 255 + 255);
(M2 => F) = (478 + 136, 723 + 255);
(M3 => F) = (478, 723);
endspecify
endspecify
endmodule
module MUX2 (O, I0, I1, S0);
@ -212,7 +212,7 @@ module DFFS (output reg Q, input D, CLK, SET);
if (SET)
Q <= 1'b1;
else
Q <= D;
Q <= D;
end
endmodule // DFFS (positive clock edge; synchronous set)
@ -388,7 +388,7 @@ endmodule // DFFNE (negative clock edge; clock enable)
module DFFNS (output reg Q, input D, CLK, SET);
parameter [0:0] INIT = 1'b1;
initial Q = INIT;
specify
(negedge CLK => (Q : D)) = (480, 660);
$setup(D, negedge CLK, 576);
@ -399,7 +399,7 @@ module DFFNS (output reg Q, input D, CLK, SET);
if (SET)
Q <= 1'b1;
else
Q <= D;
Q <= D;
end
endmodule // DFFNS (negative clock edge; synchronous set)
@ -485,7 +485,7 @@ endmodule // DFFNP (negative clock edge; asynchronous preset)
module DFFNPE (output reg Q, input D, CLK, CE, PRESET);
parameter [0:0] INIT = 1'b1;
initial Q = INIT;
specify
if (CE) (negedge CLK => (Q : D)) = (480, 660);
(PRESET => Q) = (1800, 2679);
@ -793,7 +793,7 @@ module OVIDEO(D6, D5, D4, D3, D2, D1, D0, FCLK, PCLK, RESET, Q);
parameter LSREN = "true";
endmodule
module OSER16(D15, D14, D13, D12, D11, D10,
module OSER16(D15, D14, D13, D12, D11, D10,
D9, D8, D7, D6, D5, D4, D3, D2, D1, D0, FCLK, PCLK,
RESET, Q);
output Q;
@ -918,7 +918,7 @@ RESET, CALIB, D);
parameter LSREN = "true";
endmodule
module IDES16(Q15, Q14, Q13, Q12, Q11, Q10,
module IDES16(Q15, Q14, Q13, Q12, Q11, Q10,
Q9, Q8, Q7, Q6, Q5, Q4, Q3, Q2, Q1, Q0, FCLK, PCLK,
RESET, CALIB, D);
input D;

228
techlibs/gowin/cells_xtra_gw1n.v
View file

@ -36,7 +36,7 @@ endmodule
module IODELAY(DI, SDTAP, SETN, VALUE, DF, DO);
parameter C_STATIC_DLY = 0;
parameter C_STATIC_DLY = 0;
input DI;
input SDTAP;
input SETN;
@ -47,9 +47,9 @@ endmodule
module IEM(D, CLK, RESET, MCLK, LAG, LEAD);
parameter WINSIZE = "SMALL";
parameter GSREN = "false";
parameter LSREN = "true";
parameter WINSIZE = "SMALL";
parameter GSREN = "false";
parameter LSREN = "true";
input D, CLK, RESET, MCLK;
output LAG, LEAD;
endmodule
@ -63,10 +63,10 @@ endmodule
module ROM(CLK, CE, OCE, RESET, WRE, AD, BLKSEL, DO);
parameter READ_MODE = 1'b0;
parameter BIT_WIDTH = 32;
parameter READ_MODE = 1'b0;
parameter BIT_WIDTH = 32;
parameter BLK_SEL = 3'b000;
parameter RESET_MODE = "SYNC";
parameter RESET_MODE = "SYNC";
parameter INIT_RAM_00 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_RAM_01 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_RAM_02 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
@ -132,9 +132,9 @@ parameter INIT_RAM_3D = 256'h000000000000000000000000000000000000000000000000000
parameter INIT_RAM_3E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_RAM_3F = 256'h0000000000000000000000000000000000000000000000000000000000000000;
input CLK, CE;
input OCE;
input RESET;
input WRE;
input OCE;
input RESET;
input WRE;
input [13:0] AD;
input [2:0] BLKSEL;
output [31:0] DO;
@ -142,11 +142,11 @@ endmodule
module ROMX9(CLK, CE, OCE, RESET, WRE, AD, BLKSEL, DO);
parameter READ_MODE = 1'b0;
parameter BIT_WIDTH = 36;
parameter READ_MODE = 1'b0;
parameter BIT_WIDTH = 36;
parameter BLK_SEL = 3'b000;
parameter RESET_MODE = "SYNC";
parameter INIT_RAM_00 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;
parameter RESET_MODE = "SYNC";
parameter INIT_RAM_00 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_RAM_01 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_RAM_02 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_RAM_03 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;
@ -211,9 +211,9 @@ parameter INIT_RAM_3D = 288'h000000000000000000000000000000000000000000000000000
parameter INIT_RAM_3E = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_RAM_3F = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;
input CLK, CE;
input OCE;
input RESET;
input WRE;
input OCE;
input RESET;
input WRE;
input [13:0] AD;
input [2:0] BLKSEL;
output [35:0] DO;
@ -221,9 +221,9 @@ endmodule
module pROM(CLK, CE, OCE, RESET, AD, DO);
parameter READ_MODE = 1'b0;
parameter BIT_WIDTH = 32;
parameter RESET_MODE = "SYNC";
parameter READ_MODE = 1'b0;
parameter BIT_WIDTH = 32;
parameter RESET_MODE = "SYNC";
parameter INIT_RAM_00 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_RAM_01 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_RAM_02 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
@ -289,18 +289,18 @@ parameter INIT_RAM_3D = 256'h000000000000000000000000000000000000000000000000000
parameter INIT_RAM_3E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_RAM_3F = 256'h0000000000000000000000000000000000000000000000000000000000000000;
input CLK, CE;
input OCE;
input RESET;
input OCE;
input RESET;
input [13:0] AD;
output [31:0] DO;
endmodule
module pROMX9(CLK, CE, OCE, RESET, AD, DO);
parameter READ_MODE = 1'b0;
parameter BIT_WIDTH = 36;
parameter RESET_MODE = "SYNC";
parameter INIT_RAM_00 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;
parameter READ_MODE = 1'b0;
parameter BIT_WIDTH = 36;
parameter RESET_MODE = "SYNC";
parameter INIT_RAM_00 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_RAM_01 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_RAM_02 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_RAM_03 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;
@ -365,20 +365,20 @@ parameter INIT_RAM_3D = 288'h000000000000000000000000000000000000000000000000000
parameter INIT_RAM_3E = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_RAM_3F = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;
input CLK, CE;
input OCE;
input RESET;
input OCE;
input RESET;
input [13:0] AD;
output [35:0] DO;
endmodule
module SDPB(CLKA, CEA, CLKB, CEB, OCE, RESETA, RESETB, ADA, ADB, DI, BLKSELA, BLKSELB, DO);
parameter READ_MODE = 1'b0;
parameter BIT_WIDTH_0 = 32;
parameter BIT_WIDTH_1 = 32;
parameter READ_MODE = 1'b0;
parameter BIT_WIDTH_0 = 32;
parameter BIT_WIDTH_1 = 32;
parameter BLK_SEL_0 = 3'b000;
parameter BLK_SEL_1 = 3'b000;
parameter RESET_MODE = "SYNC";
parameter RESET_MODE = "SYNC";
parameter INIT_RAM_00 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_RAM_01 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_RAM_02 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
@ -444,8 +444,8 @@ parameter INIT_RAM_3D = 256'h000000000000000000000000000000000000000000000000000
parameter INIT_RAM_3E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_RAM_3F = 256'h0000000000000000000000000000000000000000000000000000000000000000;
input CLKA, CEA, CLKB, CEB;
input OCE;
input RESETA, RESETB;
input OCE;
input RESETA, RESETB;
input [13:0] ADA, ADB;
input [31:0] DI;
input [2:0] BLKSELA, BLKSELB;
@ -454,13 +454,13 @@ endmodule
module SDPX9B(CLKA, CEA, CLKB, CEB, OCE, RESETA, RESETB, ADA, ADB, BLKSELA, BLKSELB, DI, DO);
parameter READ_MODE = 1'b0;
parameter BIT_WIDTH_0 = 36;
parameter BIT_WIDTH_1 = 36;
parameter READ_MODE = 1'b0;
parameter BIT_WIDTH_0 = 36;
parameter BIT_WIDTH_1 = 36;
parameter BLK_SEL_0 = 3'b000;
parameter BLK_SEL_1 = 3'b000;
parameter RESET_MODE = "SYNC";
parameter INIT_RAM_00 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;
parameter RESET_MODE = "SYNC";
parameter INIT_RAM_00 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_RAM_01 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_RAM_02 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_RAM_03 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;
@ -525,8 +525,8 @@ parameter INIT_RAM_3D = 288'h000000000000000000000000000000000000000000000000000
parameter INIT_RAM_3E = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_RAM_3F = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;
input CLKA, CEA, CLKB, CEB;
input OCE;
input RESETA, RESETB;
input OCE;
input RESETA, RESETB;
input [13:0] ADA, ADB;
input [2:0] BLKSELA, BLKSELB;
input [35:0] DI;
@ -535,15 +535,15 @@ endmodule
module DPB(CLKA, CEA, CLKB, CEB, OCEA, OCEB, RESETA, RESETB, WREA, WREB, ADA, ADB, BLKSELA, BLKSELB, DIA, DIB, DOA, DOB);
parameter READ_MODE0 = 1'b0;
parameter READ_MODE1 = 1'b0;
parameter WRITE_MODE0 = 2'b00;
parameter WRITE_MODE1 = 2'b00;
parameter BIT_WIDTH_0 = 16;
parameter BIT_WIDTH_1 = 16;
parameter READ_MODE0 = 1'b0;
parameter READ_MODE1 = 1'b0;
parameter WRITE_MODE0 = 2'b00;
parameter WRITE_MODE1 = 2'b00;
parameter BIT_WIDTH_0 = 16;
parameter BIT_WIDTH_1 = 16;
parameter BLK_SEL_0 = 3'b000;
parameter BLK_SEL_1 = 3'b000;
parameter RESET_MODE = "SYNC";
parameter RESET_MODE = "SYNC";
parameter INIT_RAM_00 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_RAM_01 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_RAM_02 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
@ -609,9 +609,9 @@ parameter INIT_RAM_3D = 256'h000000000000000000000000000000000000000000000000000
parameter INIT_RAM_3E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_RAM_3F = 256'h0000000000000000000000000000000000000000000000000000000000000000;
input CLKA, CEA, CLKB, CEB;
input OCEA, OCEB;
input RESETA, RESETB;
input WREA, WREB;
input OCEA, OCEB;
input RESETA, RESETB;
input WREA, WREB;
input [13:0] ADA, ADB;
input [2:0] BLKSELA, BLKSELB;
input [15:0] DIA, DIB;
@ -620,16 +620,16 @@ endmodule
module DPX9B(CLKA, CEA, CLKB, CEB, OCEA, OCEB, RESETA, RESETB, WREA, WREB, ADA, ADB, DIA, DIB, BLKSELA, BLKSELB, DOA, DOB);
parameter READ_MODE0 = 1'b0;
parameter READ_MODE1 = 1'b0;
parameter WRITE_MODE0 = 2'b00;
parameter WRITE_MODE1 = 2'b00;
parameter BIT_WIDTH_0 = 18;
parameter BIT_WIDTH_1 = 18;
parameter READ_MODE0 = 1'b0;
parameter READ_MODE1 = 1'b0;
parameter WRITE_MODE0 = 2'b00;
parameter WRITE_MODE1 = 2'b00;
parameter BIT_WIDTH_0 = 18;
parameter BIT_WIDTH_1 = 18;
parameter BLK_SEL_0 = 3'b000;
parameter BLK_SEL_1 = 3'b000;
parameter RESET_MODE = "SYNC";
parameter INIT_RAM_00 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;
parameter RESET_MODE = "SYNC";
parameter INIT_RAM_00 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_RAM_01 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_RAM_02 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_RAM_03 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;
@ -694,9 +694,9 @@ parameter INIT_RAM_3D = 288'h000000000000000000000000000000000000000000000000000
parameter INIT_RAM_3E = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_RAM_3F = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;
input CLKA, CEA, CLKB, CEB;
input OCEA, OCEB;
input RESETA, RESETB;
input WREA, WREB;
input OCEA, OCEB;
input RESETA, RESETB;
input WREA, WREB;
input [13:0] ADA, ADB;
input [17:0] DIA, DIB;
input [2:0] BLKSELA, BLKSELB;
@ -712,11 +712,11 @@ input CE,CLK,RESET;
input [17:0] SI,SBI;
output [17:0] SO,SBO;
output [17:0] DOUT;
parameter AREG = 1'b0;
parameter AREG = 1'b0;
parameter BREG = 1'b0;
parameter ADD_SUB = 1'b0;
parameter PADD_RESET_MODE = "SYNC";
parameter BSEL_MODE = 1'b1;
parameter ADD_SUB = 1'b0;
parameter PADD_RESET_MODE = "SYNC";
parameter BSEL_MODE = 1'b1;
parameter SOREG = 1'b0;
endmodule
@ -728,11 +728,11 @@ input CE,CLK,RESET;
input [8:0] SI,SBI;
output [8:0] SO,SBO;
output [8:0] DOUT;
parameter AREG = 1'b0;
parameter BREG = 1'b0;
parameter ADD_SUB = 1'b0;
parameter PADD_RESET_MODE = "SYNC";
parameter BSEL_MODE = 1'b1;
parameter AREG = 1'b0;
parameter BREG = 1'b0;
parameter ADD_SUB = 1'b0;
parameter PADD_RESET_MODE = "SYNC";
parameter BSEL_MODE = 1'b1;
parameter SOREG = 1'b0;
endmodule
@ -752,8 +752,8 @@ parameter OUT_REG = 1'b0;
parameter PIPE_REG = 1'b0;
parameter ASIGN_REG = 1'b0;
parameter BSIGN_REG = 1'b0;
parameter SOA_REG = 1'b0;
parameter MULT_RESET_MODE = "SYNC";
parameter SOA_REG = 1'b0;
parameter MULT_RESET_MODE = "SYNC";
endmodule
module MULT18X18(A, SIA, B, SIB, ASIGN, BSIGN, ASEL, BSEL, CE, CLK, RESET, DOUT, SOA, SOB);
@ -773,7 +773,7 @@ parameter PIPE_REG = 1'b0;
parameter ASIGN_REG = 1'b0;
parameter BSIGN_REG = 1'b0;
parameter SOA_REG = 1'b0;
parameter MULT_RESET_MODE = "SYNC";
parameter MULT_RESET_MODE = "SYNC";
endmodule
module MULT36X36(A, B, ASIGN, BSIGN, CE, CLK, RESET, DOUT);
@ -791,7 +791,7 @@ parameter OUT1_REG = 1'b0;
parameter PIPE_REG = 1'b0;
parameter ASIGN_REG = 1'b0;
parameter BSIGN_REG = 1'b0;
parameter MULT_RESET_MODE = "SYNC";
parameter MULT_RESET_MODE = "SYNC";
endmodule
module MULTALU36X18(A, B, C, ASIGN, BSIGN, ACCLOAD, CE, CLK, RESET, CASI, DOUT, CASO);
@ -814,9 +814,9 @@ parameter ASIGN_REG = 1'b0;
parameter BSIGN_REG = 1'b0;
parameter ACCLOAD_REG0 = 1'b0;
parameter ACCLOAD_REG1 = 1'b0;
parameter MULT_RESET_MODE = "SYNC";
parameter MULTALU36X18_MODE = 0;
parameter C_ADD_SUB = 1'b0;
parameter MULT_RESET_MODE = "SYNC";
parameter MULTALU36X18_MODE = 0;
parameter C_ADD_SUB = 1'b0;
endmodule
module MULTADDALU18X18(A0, B0, A1, B1, C, SIA, SIB, ASIGN, BSIGN, ASEL, BSEL, CASI, CE, CLK, RESET, ACCLOAD, DOUT, CASO, SOA, SOB);
@ -836,7 +836,7 @@ input ACCLOAD;
output [53:0] DOUT;
output [54:0] CASO;
output [17:0] SOA, SOB;
parameter A0REG = 1'b0;
parameter A0REG = 1'b0;
parameter A1REG = 1'b0;
parameter B0REG = 1'b0;
parameter B1REG = 1'b0;
@ -851,7 +851,7 @@ parameter ACCLOAD_REG1 = 1'b0;
parameter BSIGN0_REG = 1'b0;
parameter BSIGN1_REG = 1'b0;
parameter SOA_REG = 1'b0;
parameter B_ADD_SUB = 1'b0;
parameter B_ADD_SUB = 1'b0;
parameter C_ADD_SUB = 1'b0;
parameter MULTADDALU18X18_MODE = 0;
parameter MULT_RESET_MODE = "SYNC";
@ -875,12 +875,12 @@ parameter ASIGN_REG = 1'b0;
parameter BSIGN_REG = 1'b0;
parameter ACCLOAD_REG0 = 1'b0;
parameter ACCLOAD_REG1 = 1'b0;
parameter MULT_RESET_MODE = "SYNC";
parameter MULT_RESET_MODE = "SYNC";
parameter PIPE_REG = 1'b0;
parameter OUT_REG = 1'b0;
parameter B_ADD_SUB = 1'b0;
parameter B_ADD_SUB = 1'b0;
parameter C_ADD_SUB = 1'b0;
parameter MULTALU18X18_MODE = 0;
parameter MULTALU18X18_MODE = 0;
endmodule
module ALU54D(A, B, ASIGN, BSIGN, ACCLOAD, CASI, CLK, CE, RESET, DOUT, CASO);
@ -891,13 +891,13 @@ input [54:0] CASI;
input CLK, CE, RESET;
output [53:0] DOUT;
output [54:0] CASO;
parameter AREG = 1'b0;
parameter AREG = 1'b0;
parameter BREG = 1'b0;
parameter ASIGN_REG = 1'b0;
parameter BSIGN_REG = 1'b0;
parameter ACCLOAD_REG = 1'b0;
parameter OUT_REG = 1'b0;
parameter B_ADD_SUB = 1'b0;
parameter B_ADD_SUB = 1'b0;
parameter C_ADD_SUB = 1'b0;
parameter ALUD_MODE = 0;
parameter ALU_RESET_MODE = "SYNC";
@ -918,41 +918,41 @@ endmodule
module PLL(CLKIN, CLKFB, RESET, RESET_P, RESET_I, RESET_S, FBDSEL, IDSEL, ODSEL, PSDA, FDLY, DUTYDA, CLKOUT, LOCK, CLKOUTP, CLKOUTD, CLKOUTD3);
input CLKIN;
input CLKFB;
input RESET;
input RESET_P;
input RESET;
input RESET_P;
input RESET_I;
input RESET_S;
input [5:0] FBDSEL;
input [5:0] FBDSEL;
input [5:0] IDSEL;
input [5:0] ODSEL;
input [3:0] PSDA,FDLY;
input [3:0] PSDA,FDLY;
input [3:0] DUTYDA;
output CLKOUT;
output LOCK;
output CLKOUTP;
output CLKOUTD;
output CLKOUTD3;
parameter FCLKIN = "100.0";
parameter FCLKIN = "100.0";
parameter DYN_IDIV_SEL= "false";
parameter IDIV_SEL = 0;
parameter IDIV_SEL = 0;
parameter DYN_FBDIV_SEL= "false";
parameter FBDIV_SEL = 0;
parameter FBDIV_SEL = 0;
parameter DYN_ODIV_SEL= "false";
parameter ODIV_SEL = 8;
parameter ODIV_SEL = 8;
parameter PSDA_SEL= "0000";
parameter DYN_DA_EN = "false";
parameter DUTYDA_SEL= "1000";
parameter CLKOUT_FT_DIR = 1'b1;
parameter CLKOUTP_FT_DIR = 1'b1;
parameter CLKOUT_DLY_STEP = 0;
parameter CLKOUTP_DLY_STEP = 0;
parameter CLKFB_SEL = "internal";
parameter CLKOUT_BYPASS = "false";
parameter CLKOUTP_BYPASS = "false";
parameter CLKOUTD_BYPASS = "false";
parameter DYN_SDIV_SEL = 2;
parameter CLKOUTD_SRC = "CLKOUT";
parameter CLKOUTD3_SRC = "CLKOUT";
parameter CLKOUT_FT_DIR = 1'b1;
parameter CLKOUTP_FT_DIR = 1'b1;
parameter CLKOUT_DLY_STEP = 0;
parameter CLKOUTP_DLY_STEP = 0;
parameter CLKFB_SEL = "internal";
parameter CLKOUT_BYPASS = "false";
parameter CLKOUTP_BYPASS = "false";
parameter CLKOUTD_BYPASS = "false";
parameter DYN_SDIV_SEL = 2;
parameter CLKOUTD_SRC = "CLKOUT";
parameter CLKOUTD3_SRC = "CLKOUT";
parameter DEVICE = "GW1N-4";
endmodule
@ -1034,8 +1034,8 @@ input HCLKIN;
input RESETN;
input CALIB;
output CLKOUT;
parameter DIV_MODE = "2";
parameter GSREN = "false";
parameter DIV_MODE = "2";
parameter GSREN = "false";
endmodule
module DHCEN(CLKIN, CE, CLKOUT);
@ -1049,9 +1049,9 @@ input [7:0] DLLSTEP;
input DIR,LOADN,MOVE;
output CLKOUT;
output FLAG;
parameter DLL_INSEL = 1'b1;
parameter DLY_SIGN = 1'b0;
parameter DLY_ADJ = 0;
parameter DLL_INSEL = 1'b1;
parameter DLY_SIGN = 1'b0;
parameter DLY_ADJ = 0;
endmodule
module FLASH96K(RA, CA, PA, MODE, SEQ, ACLK, PW, RESET, PE, OE, RMODE, WMODE, RBYTESEL, WBYTESEL, DIN, DOUT);
@ -1084,7 +1084,7 @@ parameter IDLE = 4'd0,
PRO_S4 = 4'd9,
PRO_S5 = 4'd10,
RD_S1 = 4'd11,
RD_S2 = 4'd12;
RD_S2 = 4'd12;
endmodule
module FLASH608K(XADR, YADR, XE, YE, SE, ERASE, PROG, NVSTR, DIN, DOUT);
@ -1113,7 +1113,7 @@ module DCS(CLK0, CLK1, CLK2, CLK3, SELFORCE, CLKSEL, CLKOUT);
input CLK0, CLK1, CLK2, CLK3, SELFORCE;
input [3:0] CLKSEL;
output CLKOUT;
parameter DCS_MODE = "RISING";
parameter DCS_MODE = "RISING";
endmodule
module DQCE(CLKIN, CE, CLKOUT);
@ -1123,7 +1123,7 @@ output CLKOUT;
endmodule
module CLKDIV2(HCLKIN, RESETN, CLKOUT);
parameter GSREN = "false";
parameter GSREN = "false";
input HCLKIN, RESETN;
output CLKOUT;
endmodule
@ -1153,7 +1153,7 @@ parameter IDLE = 4'd0,
PRO_S4 = 4'd9,
PRO_S5 = 4'd10,
RD_S1 = 4'd11,
RD_S2 = 4'd12;
RD_S2 = 4'd12;
endmodule
module FLASH64KZ(XADR, YADR, XE, YE, SE, ERASE, PROG, NVSTR, DIN, DOUT);
@ -1175,5 +1175,5 @@ parameter IDLE = 4'd0,
PRO_S4 = 4'd9,
PRO_S5 = 4'd10,
RD_S1 = 4'd11,
RD_S2 = 4'd12;
RD_S2 = 4'd12;
endmodule

266
techlibs/gowin/cells_xtra_gw2a.v
View file

@ -36,8 +36,8 @@ endmodule
module IDDR_MEM(D, ICLK, PCLK, WADDR, RADDR, RESET, Q0, Q1);
parameter GSREN = "false";
parameter LSREN = "true";
parameter GSREN = "false";
parameter LSREN = "true";
input D, ICLK, PCLK;
input [2:0] WADDR;
input [2:0] RADDR;
@ -47,10 +47,10 @@ endmodule
module ODDR_MEM(D0, D1, TX, PCLK, TCLK, RESET, Q0, Q1);
parameter GSREN = "false";
parameter LSREN = "true";
parameter TCLK_SOURCE = "DQSW";
parameter TXCLK_POL = 1'b0;
parameter GSREN = "false";
parameter LSREN = "true";
parameter TCLK_SOURCE = "DQSW";
parameter TXCLK_POL = 1'b0;
input D0, D1;
input TX, PCLK, TCLK, RESET;
output Q0, Q1;
@ -58,8 +58,8 @@ endmodule
module IDES4_MEM(D, ICLK, FCLK, PCLK, WADDR, RADDR, RESET, CALIB, Q0, Q1, Q2, Q3);
parameter GSREN = "false";
parameter LSREN = "true";
parameter GSREN = "false";
parameter LSREN = "true";
input D, ICLK, FCLK, PCLK;
input [2:0] WADDR;
input [2:0] RADDR;
@ -69,8 +69,8 @@ endmodule
module IDES8_MEM(D, ICLK, FCLK, PCLK, WADDR, RADDR, RESET, CALIB, Q0, Q1, Q2, Q3, Q4, Q5, Q6, Q7);
parameter GSREN = "false";
parameter LSREN = "true";
parameter GSREN = "false";
parameter LSREN = "true";
input D, ICLK, FCLK, PCLK;
input [2:0] WADDR;
input [2:0] RADDR;
@ -80,11 +80,11 @@ endmodule
module OSER4_MEM(D0, D1, D2, D3, TX0, TX1, PCLK, FCLK, TCLK, RESET, Q0, Q1);
parameter GSREN = "false";
parameter LSREN = "true";
parameter HWL = "false";
parameter TCLK_SOURCE = "DQSW";
parameter TXCLK_POL = 1'b0;
parameter GSREN = "false";
parameter LSREN = "true";
parameter HWL = "false";
parameter TCLK_SOURCE = "DQSW";
parameter TXCLK_POL = 1'b0;
input D0, D1, D2, D3;
input TX0, TX1;
input PCLK, FCLK, TCLK, RESET;
@ -93,11 +93,11 @@ endmodule
module OSER8_MEM(D0, D1, D2, D3, D4, D5, D6, D7, TX0, TX1, TX2, TX3, PCLK, FCLK, TCLK, RESET, Q0, Q1);
parameter GSREN = "false";
parameter LSREN = "true";
parameter HWL = "false";
parameter TCLK_SOURCE = "DQSW";
parameter TXCLK_POL = 1'b0;
parameter GSREN = "false";
parameter LSREN = "true";
parameter HWL = "false";
parameter TCLK_SOURCE = "DQSW";
parameter TXCLK_POL = 1'b0;
input D0, D1, D2, D3, D4, D5, D6, D7;
input TX0, TX1, TX2, TX3;
input PCLK, FCLK, TCLK, RESET;
@ -106,7 +106,7 @@ endmodule
module IODELAY(DI, SDTAP, SETN, VALUE, DF, DO);
parameter C_STATIC_DLY = 0;
parameter C_STATIC_DLY = 0;
input DI;
input SDTAP;
input SETN;
@ -117,9 +117,9 @@ endmodule
module IEM(D, CLK, RESET, MCLK, LAG, LEAD);
parameter WINSIZE = "SMALL";
parameter GSREN = "false";
parameter LSREN = "true";
parameter WINSIZE = "SMALL";
parameter GSREN = "false";
parameter LSREN = "true";
input D, CLK, RESET, MCLK;
output LAG, LEAD;
endmodule
@ -133,10 +133,10 @@ endmodule
module ROM(CLK, CE, OCE, RESET, WRE, AD, BLKSEL, DO);
parameter READ_MODE = 1'b0;
parameter BIT_WIDTH = 32;
parameter READ_MODE = 1'b0;
parameter BIT_WIDTH = 32;
parameter BLK_SEL = 3'b000;
parameter RESET_MODE = "SYNC";
parameter RESET_MODE = "SYNC";
parameter INIT_RAM_00 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_RAM_01 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_RAM_02 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
@ -202,9 +202,9 @@ parameter INIT_RAM_3D = 256'h000000000000000000000000000000000000000000000000000
parameter INIT_RAM_3E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_RAM_3F = 256'h0000000000000000000000000000000000000000000000000000000000000000;
input CLK, CE;
input OCE;
input RESET;
input WRE;
input OCE;
input RESET;
input WRE;
input [13:0] AD;
input [2:0] BLKSEL;
output [31:0] DO;
@ -212,11 +212,11 @@ endmodule
module ROMX9(CLK, CE, OCE, RESET, WRE, AD, BLKSEL, DO);
parameter READ_MODE = 1'b0;
parameter BIT_WIDTH = 36;
parameter READ_MODE = 1'b0;
parameter BIT_WIDTH = 36;
parameter BLK_SEL = 3'b000;
parameter RESET_MODE = "SYNC";
parameter INIT_RAM_00 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;
parameter RESET_MODE = "SYNC";
parameter INIT_RAM_00 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_RAM_01 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_RAM_02 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_RAM_03 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;
@ -281,9 +281,9 @@ parameter INIT_RAM_3D = 288'h000000000000000000000000000000000000000000000000000
parameter INIT_RAM_3E = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_RAM_3F = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;
input CLK, CE;
input OCE;
input RESET;
input WRE;
input OCE;
input RESET;
input WRE;
input [13:0] AD;
input [2:0] BLKSEL;
output [35:0] DO;
@ -291,9 +291,9 @@ endmodule
module pROM(CLK, CE, OCE, RESET, AD, DO);
parameter READ_MODE = 1'b0;
parameter BIT_WIDTH = 32;
parameter RESET_MODE = "SYNC";
parameter READ_MODE = 1'b0;
parameter BIT_WIDTH = 32;
parameter RESET_MODE = "SYNC";
parameter INIT_RAM_00 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_RAM_01 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_RAM_02 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
@ -359,18 +359,18 @@ parameter INIT_RAM_3D = 256'h000000000000000000000000000000000000000000000000000
parameter INIT_RAM_3E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_RAM_3F = 256'h0000000000000000000000000000000000000000000000000000000000000000;
input CLK, CE;
input OCE;
input RESET;
input OCE;
input RESET;
input [13:0] AD;
output [31:0] DO;
endmodule
module pROMX9(CLK, CE, OCE, RESET, AD, DO);
parameter READ_MODE = 1'b0;
parameter BIT_WIDTH = 36;
parameter RESET_MODE = "SYNC";
parameter INIT_RAM_00 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;
parameter READ_MODE = 1'b0;
parameter BIT_WIDTH = 36;
parameter RESET_MODE = "SYNC";
parameter INIT_RAM_00 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_RAM_01 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_RAM_02 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_RAM_03 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;
@ -435,20 +435,20 @@ parameter INIT_RAM_3D = 288'h000000000000000000000000000000000000000000000000000
parameter INIT_RAM_3E = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_RAM_3F = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;
input CLK, CE;
input OCE;
input RESET;
input OCE;
input RESET;
input [13:0] AD;
output [35:0] DO;
endmodule
module SDPB(CLKA, CEA, CLKB, CEB, OCE, RESETA, RESETB, ADA, ADB, DI, BLKSELA, BLKSELB, DO);
parameter READ_MODE = 1'b0;
parameter BIT_WIDTH_0 = 32;
parameter BIT_WIDTH_1 = 32;
parameter READ_MODE = 1'b0;
parameter BIT_WIDTH_0 = 32;
parameter BIT_WIDTH_1 = 32;
parameter BLK_SEL_0 = 3'b000;
parameter BLK_SEL_1 = 3'b000;
parameter RESET_MODE = "SYNC";
parameter RESET_MODE = "SYNC";
parameter INIT_RAM_00 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_RAM_01 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_RAM_02 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
@ -514,8 +514,8 @@ parameter INIT_RAM_3D = 256'h000000000000000000000000000000000000000000000000000
parameter INIT_RAM_3E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_RAM_3F = 256'h0000000000000000000000000000000000000000000000000000000000000000;
input CLKA, CEA, CLKB, CEB;
input OCE;
input RESETA, RESETB;
input OCE;
input RESETA, RESETB;
input [13:0] ADA, ADB;
input [31:0] DI;
input [2:0] BLKSELA, BLKSELB;
@ -524,13 +524,13 @@ endmodule
module SDPX9B(CLKA, CEA, CLKB, CEB, OCE, RESETA, RESETB, ADA, ADB, BLKSELA, BLKSELB, DI, DO);
parameter READ_MODE = 1'b0;
parameter BIT_WIDTH_0 = 36;
parameter BIT_WIDTH_1 = 36;
parameter READ_MODE = 1'b0;
parameter BIT_WIDTH_0 = 36;
parameter BIT_WIDTH_1 = 36;
parameter BLK_SEL_0 = 3'b000;
parameter BLK_SEL_1 = 3'b000;
parameter RESET_MODE = "SYNC";
parameter INIT_RAM_00 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;
parameter RESET_MODE = "SYNC";
parameter INIT_RAM_00 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_RAM_01 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_RAM_02 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_RAM_03 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;
@ -595,8 +595,8 @@ parameter INIT_RAM_3D = 288'h000000000000000000000000000000000000000000000000000
parameter INIT_RAM_3E = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_RAM_3F = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;
input CLKA, CEA, CLKB, CEB;
input OCE;
input RESETA, RESETB;
input OCE;
input RESETA, RESETB;
input [13:0] ADA, ADB;
input [2:0] BLKSELA, BLKSELB;
input [35:0] DI;
@ -605,15 +605,15 @@ endmodule
module DPB(CLKA, CEA, CLKB, CEB, OCEA, OCEB, RESETA, RESETB, WREA, WREB, ADA, ADB, BLKSELA, BLKSELB, DIA, DIB, DOA, DOB);
parameter READ_MODE0 = 1'b0;
parameter READ_MODE1 = 1'b0;
parameter WRITE_MODE0 = 2'b00;
parameter WRITE_MODE1 = 2'b00;
parameter BIT_WIDTH_0 = 16;
parameter BIT_WIDTH_1 = 16;
parameter READ_MODE0 = 1'b0;
parameter READ_MODE1 = 1'b0;
parameter WRITE_MODE0 = 2'b00;
parameter WRITE_MODE1 = 2'b00;
parameter BIT_WIDTH_0 = 16;
parameter BIT_WIDTH_1 = 16;
parameter BLK_SEL_0 = 3'b000;
parameter BLK_SEL_1 = 3'b000;
parameter RESET_MODE = "SYNC";
parameter RESET_MODE = "SYNC";
parameter INIT_RAM_00 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_RAM_01 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_RAM_02 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
@ -679,9 +679,9 @@ parameter INIT_RAM_3D = 256'h000000000000000000000000000000000000000000000000000
parameter INIT_RAM_3E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_RAM_3F = 256'h0000000000000000000000000000000000000000000000000000000000000000;
input CLKA, CEA, CLKB, CEB;
input OCEA, OCEB;
input RESETA, RESETB;
input WREA, WREB;
input OCEA, OCEB;
input RESETA, RESETB;
input WREA, WREB;
input [13:0] ADA, ADB;
input [2:0] BLKSELA, BLKSELB;
input [15:0] DIA, DIB;
@ -690,16 +690,16 @@ endmodule
module DPX9B(CLKA, CEA, CLKB, CEB, OCEA, OCEB, RESETA, RESETB, WREA, WREB, ADA, ADB, DIA, DIB, BLKSELA, BLKSELB, DOA, DOB);
parameter READ_MODE0 = 1'b0;
parameter READ_MODE1 = 1'b0;
parameter WRITE_MODE0 = 2'b00;
parameter WRITE_MODE1 = 2'b00;
parameter BIT_WIDTH_0 = 18;
parameter BIT_WIDTH_1 = 18;
parameter READ_MODE0 = 1'b0;
parameter READ_MODE1 = 1'b0;
parameter WRITE_MODE0 = 2'b00;
parameter WRITE_MODE1 = 2'b00;
parameter BIT_WIDTH_0 = 18;
parameter BIT_WIDTH_1 = 18;
parameter BLK_SEL_0 = 3'b000;
parameter BLK_SEL_1 = 3'b000;
parameter RESET_MODE = "SYNC";
parameter INIT_RAM_00 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;
parameter RESET_MODE = "SYNC";
parameter INIT_RAM_00 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_RAM_01 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_RAM_02 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_RAM_03 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;
@ -764,9 +764,9 @@ parameter INIT_RAM_3D = 288'h000000000000000000000000000000000000000000000000000
parameter INIT_RAM_3E = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_RAM_3F = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;
input CLKA, CEA, CLKB, CEB;
input OCEA, OCEB;
input RESETA, RESETB;
input WREA, WREB;
input OCEA, OCEB;
input RESETA, RESETB;
input WREA, WREB;
input [13:0] ADA, ADB;
input [17:0] DIA, DIB;
input [2:0] BLKSELA, BLKSELB;
@ -782,11 +782,11 @@ input CE,CLK,RESET;
input [17:0] SI,SBI;
output [17:0] SO,SBO;
output [17:0] DOUT;
parameter AREG = 1'b0;
parameter AREG = 1'b0;
parameter BREG = 1'b0;
parameter ADD_SUB = 1'b0;
parameter PADD_RESET_MODE = "SYNC";
parameter BSEL_MODE = 1'b1;
parameter ADD_SUB = 1'b0;
parameter PADD_RESET_MODE = "SYNC";
parameter BSEL_MODE = 1'b1;
parameter SOREG = 1'b0;
endmodule
@ -798,11 +798,11 @@ input CE,CLK,RESET;
input [8:0] SI,SBI;
output [8:0] SO,SBO;
output [8:0] DOUT;
parameter AREG = 1'b0;
parameter BREG = 1'b0;
parameter ADD_SUB = 1'b0;
parameter PADD_RESET_MODE = "SYNC";
parameter BSEL_MODE = 1'b1;
parameter AREG = 1'b0;
parameter BREG = 1'b0;
parameter ADD_SUB = 1'b0;
parameter PADD_RESET_MODE = "SYNC";
parameter BSEL_MODE = 1'b1;
parameter SOREG = 1'b0;
endmodule
@ -822,8 +822,8 @@ parameter OUT_REG = 1'b0;
parameter PIPE_REG = 1'b0;
parameter ASIGN_REG = 1'b0;
parameter BSIGN_REG = 1'b0;
parameter SOA_REG = 1'b0;
parameter MULT_RESET_MODE = "SYNC";
parameter SOA_REG = 1'b0;
parameter MULT_RESET_MODE = "SYNC";
endmodule
module MULT18X18(A, SIA, B, SIB, ASIGN, BSIGN, ASEL, BSEL, CE, CLK, RESET, DOUT, SOA, SOB);
@ -843,7 +843,7 @@ parameter PIPE_REG = 1'b0;
parameter ASIGN_REG = 1'b0;
parameter BSIGN_REG = 1'b0;
parameter SOA_REG = 1'b0;
parameter MULT_RESET_MODE = "SYNC";
parameter MULT_RESET_MODE = "SYNC";
endmodule
module MULT36X36(A, B, ASIGN, BSIGN, CE, CLK, RESET, DOUT);
@ -861,7 +861,7 @@ parameter OUT1_REG = 1'b0;
parameter PIPE_REG = 1'b0;
parameter ASIGN_REG = 1'b0;
parameter BSIGN_REG = 1'b0;
parameter MULT_RESET_MODE = "SYNC";
parameter MULT_RESET_MODE = "SYNC";
endmodule
module MULTALU36X18(A, B, C, ASIGN, BSIGN, ACCLOAD, CE, CLK, RESET, CASI, DOUT, CASO);
@ -884,9 +884,9 @@ parameter ASIGN_REG = 1'b0;
parameter BSIGN_REG = 1'b0;
parameter ACCLOAD_REG0 = 1'b0;
parameter ACCLOAD_REG1 = 1'b0;
parameter MULT_RESET_MODE = "SYNC";
parameter MULTALU36X18_MODE = 0;
parameter C_ADD_SUB = 1'b0;
parameter MULT_RESET_MODE = "SYNC";
parameter MULTALU36X18_MODE = 0;
parameter C_ADD_SUB = 1'b0;
endmodule
module MULTADDALU18X18(A0, B0, A1, B1, C, SIA, SIB, ASIGN, BSIGN, ASEL, BSEL, CASI, CE, CLK, RESET, ACCLOAD, DOUT, CASO, SOA, SOB);
@ -906,7 +906,7 @@ input ACCLOAD;
output [53:0] DOUT;
output [54:0] CASO;
output [17:0] SOA, SOB;
parameter A0REG = 1'b0;
parameter A0REG = 1'b0;
parameter A1REG = 1'b0;
parameter B0REG = 1'b0;
parameter B1REG = 1'b0;
@ -921,7 +921,7 @@ parameter ACCLOAD_REG1 = 1'b0;
parameter BSIGN0_REG = 1'b0;
parameter BSIGN1_REG = 1'b0;
parameter SOA_REG = 1'b0;
parameter B_ADD_SUB = 1'b0;
parameter B_ADD_SUB = 1'b0;
parameter C_ADD_SUB = 1'b0;
parameter MULTADDALU18X18_MODE = 0;
parameter MULT_RESET_MODE = "SYNC";
@ -945,12 +945,12 @@ parameter ASIGN_REG = 1'b0;
parameter BSIGN_REG = 1'b0;
parameter ACCLOAD_REG0 = 1'b0;
parameter ACCLOAD_REG1 = 1'b0;
parameter MULT_RESET_MODE = "SYNC";
parameter MULT_RESET_MODE = "SYNC";
parameter PIPE_REG = 1'b0;
parameter OUT_REG = 1'b0;
parameter B_ADD_SUB = 1'b0;
parameter B_ADD_SUB = 1'b0;
parameter C_ADD_SUB = 1'b0;
parameter MULTALU18X18_MODE = 0;
parameter MULTALU18X18_MODE = 0;
endmodule
module ALU54D(A, B, ASIGN, BSIGN, ACCLOAD, CASI, CLK, CE, RESET, DOUT, CASO);
@ -961,13 +961,13 @@ input [54:0] CASI;
input CLK, CE, RESET;
output [53:0] DOUT;
output [54:0] CASO;
parameter AREG = 1'b0;
parameter AREG = 1'b0;
parameter BREG = 1'b0;
parameter ASIGN_REG = 1'b0;
parameter BSIGN_REG = 1'b0;
parameter ACCLOAD_REG = 1'b0;
parameter OUT_REG = 1'b0;
parameter B_ADD_SUB = 1'b0;
parameter B_ADD_SUB = 1'b0;
parameter C_ADD_SUB = 1'b0;
parameter ALUD_MODE = 0;
parameter ALU_RESET_MODE = "SYNC";
@ -1002,27 +1002,27 @@ output LOCK;
output CLKOUTP;
output CLKOUTD;
output CLKOUTD3;
parameter FCLKIN = "100.0";
parameter FCLKIN = "100.0";
parameter DYN_IDIV_SEL= "false";
parameter IDIV_SEL = 0;
parameter IDIV_SEL = 0;
parameter DYN_FBDIV_SEL= "false";
parameter FBDIV_SEL = 0;
parameter FBDIV_SEL = 0;
parameter DYN_ODIV_SEL= "false";
parameter ODIV_SEL = 8;
parameter ODIV_SEL = 8;
parameter PSDA_SEL= "0000";
parameter DYN_DA_EN = "false";
parameter DUTYDA_SEL= "1000";
parameter CLKOUT_FT_DIR = 1'b1;
parameter CLKOUTP_FT_DIR = 1'b1;
parameter CLKOUT_DLY_STEP = 0;
parameter CLKOUTP_DLY_STEP = 0;
parameter CLKFB_SEL = "internal";
parameter CLKOUT_BYPASS = "false";
parameter CLKOUTP_BYPASS = "false";
parameter CLKOUTD_BYPASS = "false";
parameter DYN_SDIV_SEL = 2;
parameter CLKOUTD_SRC = "CLKOUT";
parameter CLKOUTD3_SRC = "CLKOUT";
parameter CLKOUT_FT_DIR = 1'b1;
parameter CLKOUTP_FT_DIR = 1'b1;
parameter CLKOUT_DLY_STEP = 0;
parameter CLKOUTP_DLY_STEP = 0;
parameter CLKFB_SEL = "internal";
parameter CLKOUT_BYPASS = "false";
parameter CLKOUTP_BYPASS = "false";
parameter CLKOUTD_BYPASS = "false";
parameter DYN_SDIV_SEL = 2;
parameter CLKOUTD_SRC = "CLKOUT";
parameter CLKOUTD3_SRC = "CLKOUT";
parameter DEVICE = "GW2A-18";
endmodule
@ -1063,8 +1063,8 @@ input HCLKIN;
input RESETN;
input CALIB;
output CLKOUT;
parameter DIV_MODE = "2";
parameter GSREN = "false";
parameter DIV_MODE = "2";
parameter GSREN = "false";
endmodule
module DHCEN(CLKIN, CE, CLKOUT);
@ -1080,14 +1080,14 @@ input [2:0] RCLKSEL;
input [7:0] DLLSTEP;
input [7:0] WSTEP;
input RLOADN, RMOVE, RDIR, WLOADN, WMOVE, WDIR, HOLD;
output DQSR90, DQSW0, DQSW270;
output DQSR90, DQSW0, DQSW270;
output [2:0] RPOINT, WPOINT;
output RVALID,RBURST, RFLAG, WFLAG;
parameter FIFO_MODE_SEL = 1'b0;
parameter RD_PNTR = 3'b000;
parameter DQS_MODE = "X1";
parameter HWL = "false";
parameter GSREN = "false";
parameter FIFO_MODE_SEL = 1'b0;
parameter RD_PNTR = 3'b000;
parameter DQS_MODE = "X1";
parameter HWL = "false";
parameter GSREN = "false";
endmodule
module DLLDLY(CLKIN, DLLSTEP, DIR, LOADN, MOVE, CLKOUT, FLAG);
@ -1096,16 +1096,16 @@ input [7:0] DLLSTEP;
input DIR,LOADN,MOVE;
output CLKOUT;
output FLAG;
parameter DLL_INSEL = 1'b1;
parameter DLY_SIGN = 1'b0;
parameter DLY_ADJ = 0;
parameter DLL_INSEL = 1'b1;
parameter DLY_SIGN = 1'b0;
parameter DLY_ADJ = 0;
endmodule
module DCS(CLK0, CLK1, CLK2, CLK3, SELFORCE, CLKSEL, CLKOUT);
input CLK0, CLK1, CLK2, CLK3, SELFORCE;
input [3:0] CLKSEL;
output CLKOUT;
parameter DCS_MODE = "RISING";
parameter DCS_MODE = "RISING";
endmodule
module DQCE(CLKIN, CE, CLKOUT);
@ -1115,7 +1115,7 @@ output CLKOUT;
endmodule
module CLKDIV2(HCLKIN, RESETN, CLKOUT);
parameter GSREN = "false";
parameter GSREN = "false";
input HCLKIN, RESETN;
output CLKOUT;
endmodule

1836
techlibs/gowin/cells_xtra_gw5a.v
View file

File diff suppressed because it is too large Load diff

4
techlibs/ice40/ice40_dsp.pmg
View file

@ -33,7 +33,7 @@ code sigA sigB sigH
return sig.extract(0, i);
};
auto unextend_unsigned = [](const SigSpec &sig) {
int i;
int i;
for (i = GetSize(sig)-1; i > 0; i--)
if (sig[i] != SigBit(State::S0))
break;
@ -61,7 +61,7 @@ code sigA sigB sigH
if (i == 0)
reject;
for (int j = 0, wire_width = 0; j <= i; j++)
for (int j = 0, wire_width = 0; j <= i; j++)
if (nusers(O[j]) == 0)
wire_width++;
else {

4
techlibs/intel_alm/common/abc9_map.v
View file

@ -1,5 +1,5 @@
// This file exists to map purely-synchronous flops to ABC9 flops, while
// mapping flops with asynchronous-clear as boxes, this is because ABC9
// This file exists to map purely-synchronous flops to ABC9 flops, while
// mapping flops with asynchronous-clear as boxes, this is because ABC9
// doesn't support asynchronous-clear flops in sequential synthesis.
module MISTRAL_FF(

82
techlibs/intel_alm/common/megafunction_bb.v
View file

@ -12,81 +12,81 @@ module altera_pll
parameter operation_mode = "internal feedback",
parameter deserialization_factor = 4,
parameter data_rate = 0,
parameter sim_additional_refclk_cycles_to_lock = 0,
parameter output_clock_frequency0 = "0 ps",
parameter phase_shift0 = "0 ps",
parameter duty_cycle0 = 50,
parameter output_clock_frequency1 = "0 ps",
parameter phase_shift1 = "0 ps",
parameter duty_cycle1 = 50,
parameter output_clock_frequency2 = "0 ps",
parameter phase_shift2 = "0 ps",
parameter duty_cycle2 = 50,
parameter output_clock_frequency3 = "0 ps",
parameter phase_shift3 = "0 ps",
parameter duty_cycle3 = 50,
parameter output_clock_frequency4 = "0 ps",
parameter phase_shift4 = "0 ps",
parameter duty_cycle4 = 50,
parameter output_clock_frequency5 = "0 ps",
parameter phase_shift5 = "0 ps",
parameter duty_cycle5 = 50,
parameter output_clock_frequency6 = "0 ps",
parameter phase_shift6 = "0 ps",
parameter duty_cycle6 = 50,
parameter output_clock_frequency7 = "0 ps",
parameter phase_shift7 = "0 ps",
parameter duty_cycle7 = 50,
parameter output_clock_frequency8 = "0 ps",
parameter phase_shift8 = "0 ps",
parameter duty_cycle8 = 50,
parameter output_clock_frequency9 = "0 ps",
parameter phase_shift9 = "0 ps",
parameter duty_cycle9 = 50,
parameter duty_cycle9 = 50,
parameter output_clock_frequency10 = "0 ps",
parameter phase_shift10 = "0 ps",
parameter duty_cycle10 = 50,
parameter output_clock_frequency11 = "0 ps",
parameter phase_shift11 = "0 ps",
parameter duty_cycle11 = 50,
parameter output_clock_frequency12 = "0 ps",
parameter phase_shift12 = "0 ps",
parameter duty_cycle12 = 50,
parameter output_clock_frequency13 = "0 ps",
parameter phase_shift13 = "0 ps",
parameter duty_cycle13 = 50,
parameter output_clock_frequency14 = "0 ps",
parameter phase_shift14 = "0 ps",
parameter duty_cycle14 = 50,
parameter output_clock_frequency15 = "0 ps",
parameter phase_shift15 = "0 ps",
parameter duty_cycle15 = 50,
parameter output_clock_frequency16 = "0 ps",
parameter phase_shift16 = "0 ps",
parameter duty_cycle16 = 50,
parameter output_clock_frequency17 = "0 ps",
parameter phase_shift17 = "0 ps",
parameter duty_cycle17 = 50,
parameter clock_name_0 = "",
parameter clock_name_1 = "",
parameter clock_name_2 = "",
@ -115,126 +115,126 @@ module altera_pll
parameter n_cnt_lo_div = 1,
parameter n_cnt_bypass_en = "false",
parameter n_cnt_odd_div_duty_en = "false",
parameter c_cnt_hi_div0 = 1,
parameter c_cnt_hi_div0 = 1,
parameter c_cnt_lo_div0 = 1,
parameter c_cnt_bypass_en0 = "false",
parameter c_cnt_in_src0 = "ph_mux_clk",
parameter c_cnt_odd_div_duty_en0 = "false",
parameter c_cnt_prst0 = 1,
parameter c_cnt_ph_mux_prst0 = 0,
parameter c_cnt_hi_div1 = 1,
parameter c_cnt_hi_div1 = 1,
parameter c_cnt_lo_div1 = 1,
parameter c_cnt_bypass_en1 = "false",
parameter c_cnt_in_src1 = "ph_mux_clk",
parameter c_cnt_odd_div_duty_en1 = "false",
parameter c_cnt_prst1 = 1,
parameter c_cnt_ph_mux_prst1 = 0,
parameter c_cnt_hi_div2 = 1,
parameter c_cnt_hi_div2 = 1,
parameter c_cnt_lo_div2 = 1,
parameter c_cnt_bypass_en2 = "false",
parameter c_cnt_in_src2 = "ph_mux_clk",
parameter c_cnt_odd_div_duty_en2 = "false",
parameter c_cnt_prst2 = 1,
parameter c_cnt_ph_mux_prst2 = 0,
parameter c_cnt_hi_div3 = 1,
parameter c_cnt_hi_div3 = 1,
parameter c_cnt_lo_div3 = 1,
parameter c_cnt_bypass_en3 = "false",
parameter c_cnt_in_src3 = "ph_mux_clk",
parameter c_cnt_odd_div_duty_en3 = "false",
parameter c_cnt_prst3 = 1,
parameter c_cnt_ph_mux_prst3 = 0,
parameter c_cnt_hi_div4 = 1,
parameter c_cnt_hi_div4 = 1,
parameter c_cnt_lo_div4 = 1,
parameter c_cnt_bypass_en4 = "false",
parameter c_cnt_in_src4 = "ph_mux_clk",
parameter c_cnt_odd_div_duty_en4 = "false",
parameter c_cnt_prst4 = 1,
parameter c_cnt_ph_mux_prst4 = 0,
parameter c_cnt_hi_div5 = 1,
parameter c_cnt_hi_div5 = 1,
parameter c_cnt_lo_div5 = 1,
parameter c_cnt_bypass_en5 = "false",
parameter c_cnt_in_src5 = "ph_mux_clk",
parameter c_cnt_odd_div_duty_en5 = "false",
parameter c_cnt_prst5 = 1,
parameter c_cnt_ph_mux_prst5 = 0,
parameter c_cnt_hi_div6 = 1,
parameter c_cnt_hi_div6 = 1,
parameter c_cnt_lo_div6 = 1,
parameter c_cnt_bypass_en6 = "false",
parameter c_cnt_in_src6 = "ph_mux_clk",
parameter c_cnt_odd_div_duty_en6 = "false",
parameter c_cnt_prst6 = 1,
parameter c_cnt_ph_mux_prst6 = 0,
parameter c_cnt_hi_div7 = 1,
parameter c_cnt_hi_div7 = 1,
parameter c_cnt_lo_div7 = 1,
parameter c_cnt_bypass_en7 = "false",
parameter c_cnt_in_src7 = "ph_mux_clk",
parameter c_cnt_odd_div_duty_en7 = "false",
parameter c_cnt_prst7 = 1,
parameter c_cnt_ph_mux_prst7 = 0,
parameter c_cnt_hi_div8 = 1,
parameter c_cnt_hi_div8 = 1,
parameter c_cnt_lo_div8 = 1,
parameter c_cnt_bypass_en8 = "false",
parameter c_cnt_in_src8 = "ph_mux_clk",
parameter c_cnt_odd_div_duty_en8 = "false",
parameter c_cnt_prst8 = 1,
parameter c_cnt_ph_mux_prst8 = 0,
parameter c_cnt_hi_div9 = 1,
parameter c_cnt_hi_div9 = 1,
parameter c_cnt_lo_div9 = 1,
parameter c_cnt_bypass_en9 = "false",
parameter c_cnt_in_src9 = "ph_mux_clk",
parameter c_cnt_odd_div_duty_en9 = "false",
parameter c_cnt_prst9 = 1,
parameter c_cnt_ph_mux_prst9 = 0,
parameter c_cnt_hi_div10 = 1,
parameter c_cnt_hi_div10 = 1,
parameter c_cnt_lo_div10 = 1,
parameter c_cnt_bypass_en10 = "false",
parameter c_cnt_in_src10 = "ph_mux_clk",
parameter c_cnt_odd_div_duty_en10 = "false",
parameter c_cnt_prst10 = 1,
parameter c_cnt_ph_mux_prst10 = 0,
parameter c_cnt_hi_div11 = 1,
parameter c_cnt_hi_div11 = 1,
parameter c_cnt_lo_div11 = 1,
parameter c_cnt_bypass_en11 = "false",
parameter c_cnt_in_src11 = "ph_mux_clk",
parameter c_cnt_odd_div_duty_en11 = "false",
parameter c_cnt_prst11 = 1,
parameter c_cnt_ph_mux_prst11 = 0,
parameter c_cnt_hi_div12 = 1,
parameter c_cnt_hi_div12 = 1,
parameter c_cnt_lo_div12 = 1,
parameter c_cnt_bypass_en12 = "false",
parameter c_cnt_in_src12 = "ph_mux_clk",
parameter c_cnt_odd_div_duty_en12 = "false",
parameter c_cnt_prst12 = 1,
parameter c_cnt_ph_mux_prst12 = 0,
parameter c_cnt_hi_div13 = 1,
parameter c_cnt_hi_div13 = 1,
parameter c_cnt_lo_div13 = 1,
parameter c_cnt_bypass_en13 = "false",
parameter c_cnt_in_src13 = "ph_mux_clk",
parameter c_cnt_odd_div_duty_en13 = "false",
parameter c_cnt_prst13 = 1,
parameter c_cnt_ph_mux_prst13 = 0,
parameter c_cnt_hi_div14 = 1,
parameter c_cnt_hi_div14 = 1,
parameter c_cnt_lo_div14 = 1,
parameter c_cnt_bypass_en14 = "false",
parameter c_cnt_in_src14 = "ph_mux_clk",
parameter c_cnt_odd_div_duty_en14 = "false",
parameter c_cnt_prst14 = 1,
parameter c_cnt_ph_mux_prst14 = 0,
parameter c_cnt_hi_div15 = 1,
parameter c_cnt_hi_div15 = 1,
parameter c_cnt_lo_div15 = 1,
parameter c_cnt_bypass_en15 = "false",
parameter c_cnt_in_src15 = "ph_mux_clk",
parameter c_cnt_odd_div_duty_en15 = "false",
parameter c_cnt_prst15 = 1,
parameter c_cnt_ph_mux_prst15 = 0,
parameter c_cnt_hi_div16 = 1,
parameter c_cnt_hi_div16 = 1,
parameter c_cnt_lo_div16 = 1,
parameter c_cnt_bypass_en16 = "false",
parameter c_cnt_in_src16 = "ph_mux_clk",
parameter c_cnt_odd_div_duty_en16 = "false",
parameter c_cnt_prst16 = 1,
parameter c_cnt_ph_mux_prst16 = 0,
parameter c_cnt_hi_div17 = 1,
parameter c_cnt_hi_div17 = 1,
parameter c_cnt_lo_div17 = 1,
parameter c_cnt_bypass_en17 = "false",
parameter c_cnt_in_src17 = "ph_mux_clk",
@ -260,9 +260,9 @@ module altera_pll
parameter pll_clkin_1_src = "clk_0",
parameter pll_clk_loss_sw_en = "false",
parameter pll_auto_clk_sw_en = "false",
parameter pll_manu_clk_sw_en = "false",
parameter pll_manu_clk_sw_en = "false",
parameter pll_clk_sw_dly = 0,
parameter pll_extclk_0_cnt_src = "pll_extclk_cnt_src_vss",
parameter pll_extclk_0_cnt_src = "pll_extclk_cnt_src_vss",
parameter pll_extclk_1_cnt_src = "pll_extclk_cnt_src_vss"
) (
//input
@ -279,7 +279,7 @@ module altera_pll
input extswitch,
input adjpllin,
input cclk,
//output
output [ number_of_clocks -1 : 0] outclk,
output fboutclk,

4
techlibs/lattice/cells_sim_nexus.v
View file

@ -446,7 +446,7 @@ module OXIDE_DSP_SIM #(
input RSTA, RSTB, RSTC, RSTPIPE, RSTCTRL, RSTCIN, RSTOUT,
output wire [Z_WIDTH-1:0] Z
);
localparam M_WIDTH = (A_WIDTH+B_WIDTH);
/******** REGISTERS ********/
@ -511,7 +511,7 @@ module OXIDE_DSP_SIM #(
if (ADDSUB_USED) begin
assign pipe_d = mult_m;
assign m_ext = {{(Z_WIDTH-M_WIDTH){sgd_r2 ? pipe_q[M_WIDTH-1] : 1'b0}}, pipe_q};
assign z_d = (loadc_r2 ? c_r2 : Z) + cin_r2 + (addsub_r2 ? -m_ext : m_ext);
assign z_d = (loadc_r2 ? c_r2 : Z) + cin_r2 + (addsub_r2 ? -m_ext : m_ext);
end else begin
assign z_d = mult_m;
end

6
techlibs/lattice/dsp_map_nexus.v
View file

@ -94,10 +94,10 @@ module \$__NX_MAC18X18 (input [17:0] A, input [17:0] B, input [47:0] C, output [
.REGINPUTC("BYPASS"),
.REGOUTPUT("BYPASS")
) _TECHMAP_REPLACE_ (
.A(A),
.B(B),
.A(A),
.B(B),
.C({6'b0, C}),
.SIGNED(A_SIGNED ? 1'b1 : 1'b0),
.SIGNED(A_SIGNED ? 1'b1 : 1'b0),
.ADDSUB(SUBTRACT ? 1'b1 : 1'b0),
.Z(Y)
);

4
techlibs/lattice/lattice_dsp_nexus.cc
View file

@ -25,8 +25,8 @@ struct LatticeDspNexusPass : public Pass {
for (auto module : design->selected_modules()) {
lattice_dsp_nexus_pm pm(module, module->cells());
pm.run_nexus_mac9_4lane();
pm.run_nexus_mac9_4lane();
pm.run_nexus_mac18();
pm.run_nexus_preadd18();
}

8
techlibs/lattice/lattice_dsp_nexus.pmg
View file

@ -38,7 +38,7 @@ code
mac->setPort(\B, port(mul, \B));
mac->setPort(\C, port(add, add_C));
mac->setPort(\Y, port(add, \Y));
mac->setParam(\A_SIGNED, mul->getParam(\A_SIGNED));
mac->setParam(\A_SIGNED, mul->getParam(\A_SIGNED));
mac->setParam(\SUBTRACT, add->type == $sub ? State::S1 : State::S0);
autoremove(mul);
@ -178,9 +178,9 @@ code
{
Cell *mac = module->addCell(NEW_ID, "$__NX_MAC9X9WIDE_4LANE");
auto ext9 = [&](SigSpec s) {
s.extend_u0(9, is_signed);
auto ext9 = [&](SigSpec s) {
s.extend_u0(9, is_signed);
return s;
};

4
techlibs/lattice/lattice_gsr.cc
View file

@ -83,12 +83,12 @@ struct LatticeGsrPass : public Pass {
{
if (!cell->hasParam(ID(GSR)) || cell->getParam(ID(GSR)).decode_string() != "AUTO")
continue;
bool gsren = found_gsr;
if (cell->get_bool_attribute(ID(nogsr)))
gsren = false;
cell->setParam(ID(GSR), gsren ? Const("ENABLED") : Const("DISABLED"));
}
if (!found_gsr)

36
techlibs/microchip/LSRAM.txt
View file

@ -1,11 +1,11 @@
# ISC License
#
#
# Copyright (C) 2024 Microchip Technology Inc. and its subsidiaries
#
#
# Permission to use, copy, modify, and/or distribute this software for any
# purpose with or without fee is hereby granted, provided that the above
# copyright notice and this permission notice appear in all copies.
#
#
# THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
# WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
# MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
@ -28,9 +28,9 @@ ram block $__LSRAM_TDP_ {
init any;
# port A and port B are allowed to have different widths, but they MUST have
# WIDTH values of the same set.
# WIDTH values of the same set.
# Example: Port A has a Data Width of 1. Then Port B's Data Width must be either
# 1, 2, 4, 8, or 16 (both values are in the 'WIDTH_1' set).
# 1, 2, 4, 8, or 16 (both values are in the 'WIDTH_1' set).
# WIDTH_1 = {1, 2, 4, 8, 16}
# WIDTH_2 = {5, 10, 20}
@ -38,7 +38,7 @@ ram block $__LSRAM_TDP_ {
# "byte" must be larger than width, or width must be a multipler of "byte"
# if "byte" > WIDTH, a single enable wire is inferred
# otherwise, WIDTH/byte number of enable wires are inferred
#
#
# WIDTH = {1, 2, 4, 5, 8, 10} requires 1 enable wire
# WIDTH = {16, 20} requires 2 enable wire
@ -58,7 +58,7 @@ ram block $__LSRAM_TDP_ {
byte 8;
}
option "WIDTH_CONFIG" "ALIGN" {
# Data-Width| Address bits
# 5 | 12
# 10 | 11
@ -72,14 +72,14 @@ ram block $__LSRAM_TDP_ {
widths 5 10 20 per_port;
byte 10;
}
port srsw "A" "B" {
# read & write width must be same
width tied;
# clock polarity is rising
clock posedge;
@ -101,8 +101,8 @@ ram block $__LSRAM_TDP_ {
rdwr no_change;
# Write transparency:
# For write ports, define behaviour when another synchronous read port
# reads from the same memory cell that said write port is writing to at the same time.
# For write ports, define behaviour when another synchronous read port
# reads from the same memory cell that said write port is writing to at the same time.
wrtrans all old;
}
portoption "WRITE_MODE" "WRITE_FIRST" {
@ -123,9 +123,9 @@ ram block $__LSRAM_TDP_ {
# two-port configuration
ram block $__LSRAM_SDP_ {
# since two-port configuration is dedicated for wide-read/write,
# we want to prioritize this configuration over TDP to avoid tool picking multiple TDP RAMs
# we want to prioritize this configuration over TDP to avoid tool picking multiple TDP RAMs
# inplace of a single SDP RAM for wide read/write. This means the cost of a single SDP should
# be less than 2 TDP.
cost 129;
@ -147,10 +147,10 @@ ram block $__LSRAM_SDP_ {
# width = 32, byte-write size is 8, ignore other widths
byte 8;
}
option "WIDTH_CONFIG" "ALIGN" {
# Data-Width| Address bits
# 5 | 12
# 10 | 11
@ -166,7 +166,7 @@ ram block $__LSRAM_SDP_ {
port sw "W" {
# only consider wide write
option "WIDTH_CONFIG" "REGULAR" width 32;
option "WIDTH_CONFIG" "ALIGN" width 40;
@ -174,7 +174,7 @@ ram block $__LSRAM_SDP_ {
# only simple write supported for two-port mode
wrtrans all old;
optional;
}
port sr "R" {

16
techlibs/microchip/LSRAM_map.v
View file

@ -71,7 +71,7 @@ parameter PORT_A_WR_USED = 0;
wire [2:0] A_BLK_SEL = (PORT_A_RD_USED == 1 || PORT_A_WR_USED == 1) ? 3'b111 : 3'b000;
wire [2:0] B_BLK_SEL = (PORT_B_RD_USED == 1 || PORT_B_WR_USED == 1) ? 3'b111 : 3'b000;
// wires for write data
// wires for write data
generate
wire [19:0] A_write_data;
wire [19:0] B_write_data;
@ -115,9 +115,9 @@ wire [2:0] B_width = (PORT_B_WIDTH == 1) ? 3'b000 :
(PORT_B_WIDTH == 8 || PORT_B_WIDTH == 10) ? 3'b011 : 3'b100;
// write modes
wire [1:0] A_write_mode = PORT_A_OPTION_WRITE_MODE == "NO_CHANGE" ? 2'b00 :
wire [1:0] A_write_mode = PORT_A_OPTION_WRITE_MODE == "NO_CHANGE" ? 2'b00 :
PORT_A_OPTION_WRITE_MODE == "WRITE_FIRST" ? 2'b01 : 2'b10;
wire [1:0] B_write_mode = PORT_B_OPTION_WRITE_MODE == "NO_CHANGE" ? 2'b00 :
wire [1:0] B_write_mode = PORT_B_OPTION_WRITE_MODE == "NO_CHANGE" ? 2'b00 :
PORT_B_OPTION_WRITE_MODE == "WRITE_FIRST" ? 2'b01 : 2'b10;
RAM1K20 #(
@ -155,7 +155,7 @@ RAM1K20 #(
.B_DOUT_ARST_N(1'b1),
// Disable ECC for TDP
.ECC_EN(1'b0),
.ECC_EN(1'b0),
.ECC_BYPASS(1'b1),
.BUSY_FB(1'b0)
@ -212,7 +212,7 @@ generate
wire [1:0] A_write_EN;
wire [1:0] B_write_EN;
// write port (A provides MSB)
// write port (A provides MSB)
if (PORT_W_WIDTH == 32) begin
assign B_write_data[3:0] = PORT_W_WR_DATA[3:0];
@ -232,7 +232,7 @@ generate
assign A_write_data[9] = 1'b0;
assign A_write_data[14] = 1'b0;
assign A_write_data[19] = 1'b0;
end else if (PORT_W_WIDTH == 40) begin
assign B_write_data = PORT_W_WR_DATA[19:0];
assign A_write_data = PORT_W_WR_DATA[39:20];
@ -265,7 +265,7 @@ endgenerate
wire [2:0] A_width = (PORT_R_WIDTH == 1) ? 3'b000 :
(PORT_R_WIDTH == 2) ? 3'b001 :
(PORT_R_WIDTH == 4 || PORT_R_WIDTH == 5) ? 3'b010 :
(PORT_R_WIDTH == 8 || PORT_R_WIDTH == 10) ? 3'b011 :
(PORT_R_WIDTH == 8 || PORT_R_WIDTH == 10) ? 3'b011 :
(PORT_R_WIDTH == 16 || PORT_R_WIDTH == 20) ? 3'b100 : 3'b101;
wire [2:0] B_width = (PORT_W_WIDTH == 1) ? 3'b000 :
(PORT_W_WIDTH == 2) ? 3'b001 :
@ -311,7 +311,7 @@ RAM1K20 #(
.B_DOUT_ARST_N(1'b1),
// Disable ECC for SDP
.ECC_EN(1'b0),
.ECC_EN(1'b0),
.ECC_BYPASS(1'b1),
.BUSY_FB(1'b0)
);

2
techlibs/microchip/arith_map.v
View file

@ -48,7 +48,7 @@ module \$__microchip_XOR8_ (A, Y);
XOR8 _TECHMAP_REPLACE_.XOR8 (.A(A[0]), .B(A[1]), .C(A[2]), .D(A[3]), .E(A[4]), .F(A[5]), .G(A[6]), .H(A[7]), .Y(Y));
endmodule
(* techmap_celltype = "$alu" *)

14
techlibs/microchip/cells_sim.v
View file

@ -155,7 +155,7 @@ endmodule
// sequential elements
// MICROCHIP_SYNC_SET_DFF and MICROCHIP_SYNC_RESET_DFF are intermediate cell types to implement the simplification idiom for abc9 flow
// MICROCHIP_SYNC_SET_DFF and MICROCHIP_SYNC_RESET_DFF are intermediate cell types to implement the simplification idiom for abc9 flow
// see: https://yosyshq.readthedocs.io/projects/yosys/en/latest/yosys_internals/extending_yosys/abc_flow.html
(* abc9_flop, lib_whitebox *)
@ -196,7 +196,7 @@ module MICROCHIP_SYNC_RESET_DFF(
always @(posedge CLK) begin
if (En == 1) begin
if (Reset == 0)
if (Reset == 0)
Q <= 0;
else
Q <= D;
@ -258,7 +258,7 @@ module ARI1 (
(* abc9_carry *)
output FCO,
input A, B, C, D,
input A, B, C, D,
output Y, S
);
parameter [19:0] INIT = 20'h0;
@ -271,9 +271,9 @@ module ARI1 (
wire G = INIT[16] ? (INIT[17] ? F1 : F0) : INIT[17];
wire P = INIT[19] ? 1'b1 : (INIT[18] ? Yout : 1'b0);
assign FCO = P ? FCI : G;
specify
//pin to pin path delay
//pin to pin path delay
(A => Y ) = 472;
(B => Y ) = 407;
(C => Y ) = 238;
@ -647,7 +647,7 @@ module RAM1K20 (
input B_DOUT_EN,
input B_DOUT_SRST_N,
input B_DOUT_ARST_N,
input ECC_EN,
input ECC_EN,
input ECC_BYPASS,
output SB_CORRECT,
output DB_DETECT,
@ -684,7 +684,7 @@ module RAM64x12 (
input R_ADDR_EN,
input R_ADDR_SL_N,
input R_ADDR_SD,
input R_ADDR_AL_N,
input R_ADDR_AL_N,
input R_ADDR_AD_N,
input BLK_EN,
output [11:0] R_DATA,

24
techlibs/microchip/microchip_dsp.pmg
View file

@ -1,7 +1,7 @@
// ISC License
//
//
// Copyright (C) 2024 Microchip Technology Inc. and its subsidiaries
//
//
// Permission to use, copy, modify, and/or distribute this software for any
// purpose with or without fee is hereby granted, provided that the above
// copyright notice and this permission notice appear in all copies.
@ -16,12 +16,12 @@
// This file describes the main pattern matcher setup (of three total) that
// forms the `microchip_dsp` pass described in microchip_dsp.cc
// forms the `microchip_dsp` pass described in microchip_dsp.cc
// At a high level, it works as follows:
// ( 1) Starting from a DSP cell. Capture DSP configurations as states
// ( 2) Match for pre-adder
// ( 3) Match for post-adder
// ( 4) Match register 'A', 'B', 'D', 'P'
// ( 4) Match register 'A', 'B', 'D', 'P'
// ( 5) If post-adder and PREG both present, check if PREG feeds into post-adder.
// This indicates an accumulator situation like the ASCII diagram below:
// +--------------------------------+
@ -110,21 +110,21 @@ code bypassA bypassB bypassC bypassD bypassPASUB bypassP
endcode
// (2) Match for pre-adder
//
//
code sigA sigB sigD preAdderStatic moveBtoA
subpattern(preAddMatching);
preAdderStatic = u_preAdderStatic;
moveBtoA = false;
if (preAdderStatic) {
if (port(preAdderStatic, \Y) == sigA)
{
//used for packing
moveBtoA = true;
// sigA should be the input to the multiplier without the preAdd. sigB and sigD should be
//the preAdd inputs. If our "A" input into the multiplier is from the preAdd (not sigA), then
// sigA should be the input to the multiplier without the preAdd. sigB and sigD should be
//the preAdd inputs. If our "A" input into the multiplier is from the preAdd (not sigA), then
// we basically swap it.
sigA = sigB;
}
@ -144,7 +144,7 @@ code postAdderStatic sigP sigC
if (postAdderStatic) {
//sigC will be whichever input to the postAdder that is NOT from the multiplier
// u_postAddAB is the input to the postAdder from the multiplier
// u_postAddAB is the input to the postAdder from the multiplier
sigC = port(postAdderStatic, u_postAddAB == \A ? \B : \A);
sigP = port(postAdderStatic, \Y);
}
@ -269,7 +269,7 @@ code
if (postAdd)
{
if (postAdd->type.in($sub) && postAddAB == \A) {
// if $sub, the multiplier output must match to $sub.B, otherwise no match
// if $sub, the multiplier output must match to $sub.B, otherwise no match
} else {
u_postAddAB = postAddAB;
u_postAdderStatic = postAdd;
@ -286,11 +286,11 @@ endcode
subpattern preAddMatching
arg sigA sigB sigD bypassB bypassD bypassPASUB
code
code
u_preAdderStatic = nullptr;
// Ensure that preAdder not already used
// Assume we can inspect port D to see if its all zeros.
// Assume we can inspect port D to see if its all zeros.
if (!(sigD.empty() || sigD.is_fully_zero())) reject;
if (!bypassB.is_fully_ones()) reject;
if (!bypassD.is_fully_ones()) reject;

6
techlibs/microchip/microchip_dsp_CREG.pmg
View file

@ -1,7 +1,7 @@
// ISC License
//
//
// Copyright (C) 2024 Microchip Technology Inc. and its subsidiaries
//
//
// Permission to use, copy, modify, and/or distribute this software for any
// purpose with or without fee is hereby granted, provided that the above
// copyright notice and this permission notice appear in all copies.
@ -164,5 +164,5 @@ code argQ
argQ = Q;
dffD.replace(argQ, D);
}
endcode

18
techlibs/microchip/microchip_dsp_cascade.pmg
View file

@ -1,7 +1,7 @@
// ISC License
//
//
// Copyright (C) 2024 Microchip Technology Inc. and its subsidiaries
//
//
// Permission to use, copy, modify, and/or distribute this software for any
// purpose with or without fee is hereby granted, provided that the above
// copyright notice and this permission notice appear in all copies.
@ -18,10 +18,10 @@
// This file describes the third of three pattern matcher setups that
// forms the `microchip_dsp` pass described in microchip_dsp.cc
// At a high level, it works as follows:
// (1) Starting from a DSP cell that
// (1) Starting from a DSP cell that
// (a) CDIN_FDBK_SEL is set to default "00"
// (b) doesn't already use the 'PCOUT' port
// (2) Match another DSP cell that
// (2) Match another DSP cell that
// (a) does not have the CREG enabled,
// (b) 'C' port is driven by the 'P' output of the previous DSP cell
// (c) has its 'PCIN' port unused
@ -72,7 +72,7 @@ code
};
endcode
// (1) Starting from a DSP cell that
// (1) Starting from a DSP cell that
// (a) CDIN_FDBK_SEL is set to default "00"
// (b) doesn't already use the 'PCOUT' port
match first
@ -133,7 +133,7 @@ finally
{
dsp_pcin->setPort(\ARSHFT17, State::S1);
}
log_debug("PCOUT -> PCIN cascade for %s -> %s\n", dsp, dsp_pcin);
@ -154,7 +154,7 @@ subpattern tail
arg first
arg next
// (2) Match another DSP cell that
// (2) Match another DSP cell that
// (a) does not have the CREG enabled,
// (b) 'C' port is driven by the 'P' output of the previous DSP cell
// (c) has its 'PCIN' port unused
@ -213,7 +213,7 @@ code
chain.emplace_back(next, shift);
visited.insert(next);
SigSpec sigC = unextend(port(next, \C));
// Make sure driverDSP.P === DSP.C
@ -231,6 +231,6 @@ finally
visited.erase(next);
chain.pop_back();
}
endcode

10
techlibs/microchip/polarfire_dsp_map.v
View file

@ -27,9 +27,9 @@ module \$__MUL18X18 (input [17:0] A, input [17:0] B, output [35:0] Y);
// For pin descriptions, see Section 9 of PolarFire FPGA Macro Library Guide:
// https://coredocs.s3.amazonaws.com/Libero/2021_2/Tool/pf_mlg.pdf
MACC_PA _TECHMAP_REPLACE_ (
.DOTP(1'b0),
.SIMD(1'b0),
.OVFL_CARRYOUT_SEL(1'b0),
.DOTP(1'b0),
.SIMD(1'b0),
.OVFL_CARRYOUT_SEL(1'b0),
.AL_N(1'b1),
.A(A),
@ -47,7 +47,7 @@ module \$__MUL18X18 (input [17:0] A, input [17:0] B, output [35:0] Y);
.D_ARST_N(1'b1),
.D_SRST_N(1'b1),
.D_EN(1'b1),
.CARRYIN(1'b0),
.C(48'b0),
.C_BYPASS(1'b1),
@ -55,7 +55,7 @@ module \$__MUL18X18 (input [17:0] A, input [17:0] B, output [35:0] Y);
.C_SRST_N(1'b1),
.C_EN(1'b1),
.P(P_48),
.P_BYPASS(1'b1),

12
techlibs/microchip/uSRAM.txt
View file

@ -1,11 +1,11 @@
# ISC License
#
#
# Copyright (C) 2024 Microchip Technology Inc. and its subsidiaries
#
#
# Permission to use, copy, modify, and/or distribute this software for any
# purpose with or without fee is hereby granted, provided that the above
# copyright notice and this permission notice appear in all copies.
#
#
# THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
# WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
# MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
@ -30,10 +30,10 @@ ram block $__uSRAM_AR_ {
port sw "W" {
clock posedge;
# collision not supported, but write takes precedence and read data is invalid while writing to
# collision not supported, but write takes precedence and read data is invalid while writing to
# the same address
wrtrans all new;
optional;
}
port ar "R" {
@ -57,7 +57,7 @@ widths 12 per_port;
# collision not supported
wrtrans all new;
optional;
}
port sr "R" {

4
techlibs/microchip/uSRAM_map.v
View file

@ -48,7 +48,7 @@ RAM64x12 #(
.R_ADDR_EN(1'b0),
.R_ADDR_SL_N(1'b1),
.R_ADDR_SD(1'b0),
.R_ADDR_AL_N(1'b1),
.R_ADDR_AL_N(1'b1),
.R_ADDR_AD_N(1'b0),
.BLK_EN(PORT_R_USED ? 1'b1 : 1'b0),
.R_DATA(PORT_R_RD_DATA),
@ -103,7 +103,7 @@ RAM64x12 #(
.R_ADDR_EN(PORT_R_RD_EN),
.R_ADDR_SL_N(1'b1),
.R_ADDR_SD(1'b0),
.R_ADDR_AL_N(1'b1),
.R_ADDR_AL_N(1'b1),
.R_ADDR_AD_N(1'b0),
.BLK_EN(PORT_R_USED ? 1'b1 : 1'b0),
.R_DATA(PORT_R_RD_DATA),

2
techlibs/nanoxplore/brams_init.vh
View file

@ -3,7 +3,7 @@ function [409600-1:0] bram_init_to_string;
input integer blocks;
input integer width;
reg [409600-1:0] temp; // (49152+2048)*8 48K bit data + 2k commas
reg [24-1:0] temp2;
reg [24-1:0] temp2;
integer i;
integer j;
begin

8
techlibs/nanoxplore/cells_sim_u.v
View file

@ -172,15 +172,15 @@ module NX_RFB_U(WCK, I1, I2, I3, I4, I5, I6, I7, I8, I9, I10, I11, I12, I13, I14
end
wire [ADDR_WIDTH-1:0] WA = (mode==2) ? { WA6, WA5, WA4, WA3, WA2, WA1 } : { WA5, WA4, WA3, WA2, WA1 };
wire [36-1:0] O = { O36, O35, O34, O33, O32, O31, O30, O29, O28,
O27, O26, O25, O24, O23, O22, O21, O20, O19,
wire [36-1:0] O = { O36, O35, O34, O33, O32, O31, O30, O29, O28,
O27, O26, O25, O24, O23, O22, O21, O20, O19,
O18, O17, O16, O15, O14, O13, O12, O11, O10,
O9, O8, O7, O6, O5, O4, O3, O2, O1 };
wire [36-1:0] I = { I36, I35, I34, I33, I32, I31, I30, I29, I28,
I27, I26, I25, I24, I23, I22, I21, I20, I19,
I18, I17, I16, I15, I14, I13, I12, I11, I10,
I9, I8, I7, I6, I5, I4, I3, I2, I1 };
generate
generate
if (mode==0) begin
assign O = mem[{ RA5, RA4, RA3, RA2, RA1 }];
end
@ -196,7 +196,7 @@ module NX_RFB_U(WCK, I1, I2, I3, I4, I5, I6, I7, I8, I9, I10, I11, I12, I13, I14
else if (mode==4) begin
assign O = { mem[{ RA10, RA9, RA8, RA7, RA6 }], mem[{ RA5, RA4, RA3, RA2, RA1 }] };
end
else
else
$error("Unknown NX_RFB_U mode");
endgenerate

8
techlibs/nanoxplore/nx_carry.cc
View file

@ -52,7 +52,7 @@ static void nx_carry_chain(Module *module)
{
if (cell->type == ID(NX_CY_1BIT)) {
if (cell->getParam(ID(first)).as_int() == 0) continue;
vector<Cell*> chain;
Cell *current = cell;
chain.push_back(current);
@ -124,8 +124,8 @@ static void nx_carry_chain(Module *module)
}
cell->setPort(names_A[j], get_bit_or_zero(c.second.at(i)->getPort(ID(A))));
cell->setPort(names_B[j], get_bit_or_zero(c.second.at(i)->getPort(ID(B))));
if (c.second.at(i)->hasPort(ID(S)))
if (c.second.at(i)->hasPort(ID(S)))
cell->setPort(names_S[j], c.second.at(i)->getPort(ID(S)));
j = (j + 1) % 4;
@ -148,7 +148,7 @@ struct NXCarryPass : public Pass {
void execute(std::vector<std::string> args, RTLIL::Design *design) override
{
log_header(design, "Executing NX_CARRY pass.\n");
size_t argidx;
for (argidx = 1; argidx < args.size(); argidx++)
{

2
techlibs/nanoxplore/rf_rams_map_l.v
View file

@ -2,7 +2,7 @@ module $__NX_RFB_L_ (
input PORT_W_CLK,
input PORT_W_WR_EN,
input [5:0] PORT_W_ADDR,
input [15:0] PORT_W_WR_DATA,
input [15:0] PORT_W_WR_DATA,
input PORT_R_CLK,
input PORT_R_RD_EN,
input [5:0] PORT_R_ADDR,

2
techlibs/nanoxplore/rf_rams_map_m.v
View file

@ -2,7 +2,7 @@ module $__NX_RFB_M_ (
input PORT_W_CLK,
input PORT_W_WR_EN,
input [5:0] PORT_W_ADDR,
input [15:0] PORT_W_WR_DATA,
input [15:0] PORT_W_WR_DATA,
input PORT_R_CLK,
input PORT_R_RD_EN,
input [5:0] PORT_R_ADDR,

6
techlibs/nanoxplore/synth_nanoxplore.cc
View file

@ -1,8 +1,8 @@
/*
* yosys -- Yosys Open SYnthesis Suite
*
* Copyright (C) 2024 Hannah Ravensloft <lofty@yosyshq.com>
* Copyright (C) 2024 Miodrag Milanovic <micko@yosyshq.com>
* Copyright (C) 2024 Hannah Ravensloft <lofty@yosyshq.com>
* Copyright (C) 2024 Miodrag Milanovic <micko@yosyshq.com>
*
* Permission to use, copy, modify, and/or distribute this software for any
* purpose with or without fee is hereby granted, provided that the above
@ -217,7 +217,7 @@ struct SynthNanoXplorePass : public ScriptPass
postfix = "_m";
} else if (family == "large") {
postfix = "_l";
} else
} else
log_cmd_error("Invalid NanoXplore -family setting: '%s'.\n", family);
if (!design->full_selection())

4
techlibs/quicklogic/pp3/abc9_map.v
View file

@ -1,5 +1,5 @@
// This file exists to map purely-synchronous flops to ABC9 flops, while
// mapping flops with asynchronous-set/clear as boxes, this is because ABC9
// This file exists to map purely-synchronous flops to ABC9 flops, while
// mapping flops with asynchronous-set/clear as boxes, this is because ABC9
// doesn't support asynchronous-set/clear flops in sequential synthesis.
module dffepc (

2
techlibs/quicklogic/ql_bram_merge.cc
View file

@ -180,7 +180,7 @@ struct QlBramMergeWorker {
};
struct QlBramMergePass : public Pass {
QlBramMergePass() : Pass("ql_bram_merge", "Infers QuickLogic k6n10f BRAM pairs that can operate independently") {}
void help() override

6
techlibs/quicklogic/ql_bram_types.cc
View file

@ -29,7 +29,7 @@ PRIVATE_NAMESPACE_BEGIN
struct QlBramTypesPass : public Pass {
QlBramTypesPass() : Pass("ql_bram_types", "Change TDP36K type to subtypes") {}
void help() override
@ -81,7 +81,7 @@ struct QlBramTypesPass : public Pass {
{
if (cell->type != ID(TDP36K) || !cell->hasParam(ID(MODE_BITS)))
continue;
RTLIL::Const mode_bits = cell->getParam(ID(MODE_BITS));
bool split = mode_bits.extract(80).as_bool();
@ -139,7 +139,7 @@ struct QlBramTypesPass : public Pass {
type += "SYNC_";
else
type += "ASYNC_";
} else
} else
type += "_BRAM_";
if (split) {

2
techlibs/quicklogic/qlf_k6n10f/libmap_brams_map.v
View file

@ -15,7 +15,7 @@
// SPDX-License-Identifier: Apache-2.0
module \$__QLF_TDP36K (PORT_A_CLK, PORT_A_ADDR, PORT_A_WR_DATA, PORT_A_WR_EN, PORT_A_WR_BE, PORT_A_CLK_EN, PORT_A_RD_DATA,
PORT_B_CLK, PORT_B_ADDR, PORT_B_WR_DATA, PORT_B_WR_EN, PORT_B_WR_BE, PORT_B_CLK_EN, PORT_B_RD_DATA);
PORT_B_CLK, PORT_B_ADDR, PORT_B_WR_DATA, PORT_B_WR_EN, PORT_B_WR_BE, PORT_B_CLK_EN, PORT_B_RD_DATA);
parameter INIT = 0;

2
techlibs/quicklogic/synth_quicklogic.cc
View file

@ -342,7 +342,7 @@ struct SynthQuickLogicPass : public ScriptPass {
run("clean");
run("opt_lut");
}
if (check_label("iomap", "(for qlf_k6n10f, skip if -noioff)") && (family == "qlf_k6n10f" || help_mode)) {
if (ioff || help_mode) {
run("ql_ioff");

4
techlibs/sf2/NOTES.txt
View file

@ -51,8 +51,8 @@ Then you can use the normal flow. This is done by the run_yosys.tcl:
----------- run_yosys.tcl --------------
open_project -file {./top.prjx}
run_tool -name {PLACEROUTE}
run_tool -name {PROGRAMDEVICE}
run_tool -name {PLACEROUTE}
run_tool -name {PROGRAMDEVICE}
-----------------------------------------

2
techlibs/xilinx/tests/test_dsp_model.v
View file

@ -178,7 +178,7 @@ module testbench;
{RSTA, RSTALLCARRYIN, RSTALUMODE, RSTB, RSTC, RSTCTRL, RSTD, RSTINMODE, RSTM, RSTP} = $urandom & $urandom & $urandom & $urandom & $urandom & $urandom;
{ALUMODE, INMODE} = $urandom;
CARRYINSEL = $urandom & $urandom & $urandom;
OPMODE = $urandom;
OPMODE = $urandom;
if ($urandom & 1'b1)
OPMODE[3:0] = 4'b0101; // test multiply more than other modes
{CARRYCASCIN, CARRYIN, MULTSIGNIN} = $urandom;