Remove trailing whitespaces

docs/source/using_yosys/synthesis/cell_libs.rst

@@ -18,7 +18,7 @@ detail in the :doc:`/getting_started/example_synth` document.
    The :file:`counter.ys` script includes the commands used to generate the
    images in this document.  Code snippets in this document skip these commands;
    including line numbers to allow the reader to follow along with the source.
-   
+
    To learn more about these commands, check out :ref:`interactive_show`.
 
 .. _example project: https://github.com/YosysHQ/yosys/tree/main/docs/source/code_examples/intro
@@ -37,7 +37,7 @@ First, let's quickly look at the design:
 This is a simple counter with reset and enable.  If the reset signal, ``rst``,
 is high then the counter will reset to 0.  Otherwise, if the enable signal,
 ``en``, is high then the ``count`` register will increment by 1 each rising edge
-of the clock, ``clk``.  
+of the clock, ``clk``.
 
 Loading the design
 ~~~~~~~~~~~~~~~~~~

docs/source/using_yosys/synthesis/extract.rst

@@ -24,7 +24,7 @@ Example code can be found in |code_examples/macc|_.
 
 .. figure:: /_images/code_examples/macc/macc_simple_test_00a.*
     :class: width-helper invert-helper
-    
+
     before `extract`
 
 .. literalinclude:: /code_examples/macc/macc_simple_test.ys
@@ -33,7 +33,7 @@ Example code can be found in |code_examples/macc|_.
 
 .. figure:: /_images/code_examples/macc/macc_simple_test_00b.*
     :class: width-helper invert-helper
-    
+
     after `extract`
 
 .. literalinclude:: /code_examples/macc/macc_simple_test.v

docs/source/using_yosys/synthesis/fsm.rst

@@ -92,7 +92,7 @@ transition table. For each state:
 3. Set the state signal to the current state
 4. Try to evaluate the next state and control output
 5. If step 4 was not successful:
-   
+
    -  Recursively goto step 4 with the offending stop-signal set to 0.
    -  Recursively goto step 4 with the offending stop-signal set to 1.
 

docs/source/using_yosys/synthesis/memory.rst

@@ -122,7 +122,7 @@ to four memory primitive classes available for selection:
   - Can handle arbitrary number and kind of read ports
 
 - LUT RAM (aka distributed RAM): uses LUT storage as RAM
-  
+
   - Supported on most FPGAs (with notable exception of ice40)
   - Usually has one synchronous write port, one or more asynchronous read ports
   - Small
@@ -141,7 +141,7 @@ to four memory primitive classes available for selection:
 - Huge RAM:
 
   - Only supported on several targets:
-    
+
     - Some Xilinx UltraScale devices (UltraRAM)
 
       - Two ports, both with mutually exclusive synchronous read and write
@@ -154,7 +154,7 @@ to four memory primitive classes available for selection:
       - Does not support initial data
 
     - Nexus (large RAM)
-      
+
       - Two ports, both with mutually exclusive synchronous read and write
       - Single clock
 
@@ -304,7 +304,7 @@ Synchronous SDP with undefined collision behavior
 
 		if (read_enable) begin
 			read_data <= mem[read_addr];
-		
+
 		if (write_enable && read_addr == write_addr)
 			// this if block
 			read_data <= 'x;
@@ -322,7 +322,7 @@ Synchronous SDP with undefined collision behavior
 		if (write_enable)
 			mem[write_addr] <= write_data;
 
-		if (read_enable) 
+		if (read_enable)
 			read_data <= mem[read_addr];
 	end
 
@@ -446,7 +446,7 @@ Synchronous single-port RAM with write-first behavior
 		if (read_enable)
 			if (write_enable)
 				read_data <= write_data;
-			else 
+			else
 				read_data <= mem[addr];
 	end
 

docs/source/using_yosys/synthesis/techmap_synth.rst

@@ -1,4 +1,4 @@
-Technology mapping 
+Technology mapping
 ==================
 
 .. todo:: less academic, check text is coherent