Remove trailing whitespaces

docs/source/using_yosys/more_scripting/interactive_investigation.rst

@@ -56,7 +56,7 @@ is shown.
 
 .. figure:: /_images/code_examples/show/example_first.*
    :class: width-helper invert-helper
-   
+
    Output of the first `show` command in :numref:`example_ys`
 
 The first output shows the design directly after being read by the Verilog
@@ -88,7 +88,7 @@ multiplexer and a d-type flip-flop, which brings us to the second diagram:
 
 .. figure:: /_images/code_examples/show/example_second.*
    :class: width-helper invert-helper
-   
+
    Output of the second `show` command in :numref:`example_ys`
 
 The Rhombus shape to the right is a dangling wire. (Wire nodes are only shown if
@@ -106,14 +106,14 @@ operations, it is therefore recommended to always call `clean` before calling
 `show`.
 
 In this script we directly call `opt` as the next step, which finally leads us
-to the third diagram: 
+to the third diagram:
 
 .. figure:: /_images/code_examples/show/example_third.*
    :class: width-helper invert-helper
    :name: example_out
-   
+
    Output of the third `show` command in :ref:`example_ys`
-   
+
 Here we see that the `opt` command not only has removed the artifacts left
 behind by `proc`, but also determined correctly that it can remove the first
 `$mux` cell without changing the behavior of the circuit.
@@ -167,7 +167,7 @@ mapped to a cell library:
    :class: width-helper invert-helper
    :name: first_pitfall
 
-   A half-adder built from simple CMOS gates, demonstrating common pitfalls when 
+   A half-adder built from simple CMOS gates, demonstrating common pitfalls when
    using `show`
 
 .. literalinclude:: /code_examples/show/cmos.ys
@@ -176,7 +176,7 @@ mapped to a cell library:
    :end-at: cmos_00
    :name: pitfall_code
    :caption: Generating :numref:`first_pitfall`
-   
+
 First, Yosys did not have access to the cell library when this diagram was
 generated, resulting in all cell ports defaulting to being inputs. This is why
 all ports are drawn on the left side the cells are awkwardly arranged in a large
@@ -248,7 +248,7 @@ command already fails to verify, it is better to troubleshoot the coarse-grain
 version of the circuit before `techmap` than the gate-level circuit after
 `techmap`.
 
-.. Note:: 
+.. Note::
 
    It is generally recommended to verify the internal state of a design by
    writing it to a Verilog file using :yoscrypt:`write_verilog -noexpr` and
@@ -327,7 +327,7 @@ tools).
 - :cmd:title:`dump`.
 - :cmd:title:`add` and :cmd:title:`delete` can be used to modify and reorganize
   a design dynamically.
-  
+
 The code used is included in the Yosys code base under
 |code_examples/scrambler|_.
 
@@ -438,7 +438,7 @@ Recall the ``memdemo`` design from :ref:`advanced_logic_cones`:
 
 .. figure:: /_images/code_examples/selections/memdemo_00.*
    :class: width-helper invert-helper
-   
+
    ``memdemo``
 
 Because this produces a rather large circuit, it can be useful to split it into
@@ -459,18 +459,18 @@ below.
 
 .. figure:: /_images/code_examples/selections/submod_02.*
    :class: width-helper invert-helper
-   
+
    ``outstage``
 
 .. figure:: /_images/code_examples/selections/submod_03.*
    :class: width-helper invert-helper
    :name: selstage
-   
+
    ``selstage``
 
 .. figure:: /_images/code_examples/selections/submod_01.*
    :class: width-helper invert-helper
-   
+
    ``scramble``
 
 Evaluation of combinatorial circuits
@@ -541,9 +541,9 @@ to solve this kind of problems.
 
 .. _MiniSAT: http://minisat.se/
 
-.. note:: 
-    
-    While it is possible to perform model checking directly in Yosys, it 
+.. note::
+
+    While it is possible to perform model checking directly in Yosys, it
     is highly recommended to use SBY or EQY for formal hardware verification.
 
 The `sat` command works very similar to the `eval` command. The main difference

docs/source/using_yosys/more_scripting/load_design.rst

@@ -81,7 +81,7 @@ Yosys frontends
    'Frontend' here means that the command is implemented as a sub-class of
    ``RTLIL::Frontend``, as opposed to the usual ``RTLIL::Pass``.
 
-.. todo:: link note to as-yet non-existent section on ``RTLIL::Pass`` under 
+.. todo:: link note to as-yet non-existent section on ``RTLIL::Pass`` under
           :doc:`/yosys_internals/extending_yosys/index`
 
 The `read_verilog` command

docs/source/using_yosys/more_scripting/selections.rst

@@ -35,8 +35,8 @@ selection; while :yoscrypt:`delete foobar` will only delete the module foobar.
 If no `select` command has been made, then the "current selection" will be the
 whole design.
 
-.. note:: Many of the examples on this page make use of the `show` 
-   command to visually demonstrate the effect of selections.  For a more 
+.. note:: Many of the examples on this page make use of the `show`
+   command to visually demonstrate the effect of selections.  For a more
    detailed look at this command, refer to :ref:`interactive_show`.
 
 How to make a selection
@@ -106,7 +106,7 @@ glance. When it is called with multiple arguments, each argument is evaluated
 and pushed separately on a stack. After all arguments have been processed it
 simply creates the union of all elements on the stack. So :yoscrypt:`select
 t:$add a:foo` will select all `$add` cells and all objects with the ``foo``
-attribute set:   
+attribute set:
 
 .. literalinclude:: /code_examples/selections/foobaraddsub.v
    :caption: Test module for operations on selections
@@ -130,7 +130,7 @@ select all `$add` cells that have the ``foo`` attribute set:
 
 .. code-block::
    :caption: Output for command ``select t:$add a:foo %i -list`` on :numref:`foobaraddsub`
-   
+
    yosys> select t:$add a:foo %i -list
    foobaraddsub/$add$foobaraddsub.v:4$1
 
@@ -282,7 +282,7 @@ provided :file:`memdemo.v` is in the same directory. We can now change to the
 .. figure:: /_images/code_examples/selections/memdemo_00.*
    :class: width-helper invert-helper
    :name: memdemo_00
-   
+
    Complete circuit diagram for the design shown in :numref:`memdemo_src`
 
 There's a lot going on there, but maybe we are only interested in the tree of
@@ -293,7 +293,7 @@ cones`_ from above, we can use :yoscrypt:`show y %ci2`:
 .. figure:: /_images/code_examples/selections/memdemo_01.*
    :class: width-helper invert-helper
    :name: memdemo_01
-   
+
    Output of :yoscrypt:`show y %ci2`
 
 From this we would learn that ``y`` is driven by a `$dff` cell, that ``y`` is
@@ -305,7 +305,7 @@ start of the name).  Let's go a bit further now and try :yoscrypt:`show y %ci5`:
 .. figure:: /_images/code_examples/selections/memdemo_02.*
    :class: width-helper invert-helper
    :name: memdemo_02
-   
+
    Output of :yoscrypt:`show y %ci5`
 
 That's starting to get a bit messy, so maybe we want to ignore the mux select
@@ -319,7 +319,7 @@ type with :yoscrypt:`show y %ci5:-$mux[S]`:
 .. figure:: /_images/code_examples/selections/memdemo_03.*
    :class: width-helper invert-helper
    :name: memdemo_03
-   
+
    Output of :yoscrypt:`show y %ci5:-$mux[S]`
 
 We could use a command such as :yoscrypt:`show y %ci2:+$dff[Q,D]
@@ -330,7 +330,7 @@ multiplexer select inputs and flip-flop cells:
 .. figure:: /_images/code_examples/selections/memdemo_05.*
    :class: width-helper invert-helper
    :name: memdemo_05
-   
+
    Output of ``show y %ci2:+$dff[Q,D] %ci*:-$mux[S]:-$dff``
 
 Or we could use :yoscrypt:`show y %ci*:-[CLK,S]:+$dff:+$mux` instead, following
@@ -342,7 +342,7 @@ ignoring any ports named ``CLK`` or ``S``:
 .. figure:: /_images/code_examples/selections/memdemo_04.*
    :class: width-helper invert-helper
    :name: memdemo_04
-   
+
    Output of :yoscrypt:`show y %ci*:-[CLK,S]:+$dff,$mux`
 
 Similar to ``%ci`` exists an action ``%co`` to select output cones that accepts

docs/source/using_yosys/synthesis/cell_libs.rst

@@ -18,7 +18,7 @@ detail in the :doc:`/getting_started/example_synth` document.
    The :file:`counter.ys` script includes the commands used to generate the
    images in this document.  Code snippets in this document skip these commands;
    including line numbers to allow the reader to follow along with the source.
-   
+
    To learn more about these commands, check out :ref:`interactive_show`.
 
 .. _example project: https://github.com/YosysHQ/yosys/tree/main/docs/source/code_examples/intro
@@ -37,7 +37,7 @@ First, let's quickly look at the design:
 This is a simple counter with reset and enable.  If the reset signal, ``rst``,
 is high then the counter will reset to 0.  Otherwise, if the enable signal,
 ``en``, is high then the ``count`` register will increment by 1 each rising edge
-of the clock, ``clk``.  
+of the clock, ``clk``.
 
 Loading the design
 ~~~~~~~~~~~~~~~~~~

docs/source/using_yosys/synthesis/extract.rst

@@ -24,7 +24,7 @@ Example code can be found in |code_examples/macc|_.
 
 .. figure:: /_images/code_examples/macc/macc_simple_test_00a.*
     :class: width-helper invert-helper
-    
+
     before `extract`
 
 .. literalinclude:: /code_examples/macc/macc_simple_test.ys
@@ -33,7 +33,7 @@ Example code can be found in |code_examples/macc|_.
 
 .. figure:: /_images/code_examples/macc/macc_simple_test_00b.*
     :class: width-helper invert-helper
-    
+
     after `extract`
 
 .. literalinclude:: /code_examples/macc/macc_simple_test.v

docs/source/using_yosys/synthesis/fsm.rst

@@ -92,7 +92,7 @@ transition table. For each state:
 3. Set the state signal to the current state
 4. Try to evaluate the next state and control output
 5. If step 4 was not successful:
-   
+
    -  Recursively goto step 4 with the offending stop-signal set to 0.
    -  Recursively goto step 4 with the offending stop-signal set to 1.
 

docs/source/using_yosys/synthesis/memory.rst

@@ -122,7 +122,7 @@ to four memory primitive classes available for selection:
   - Can handle arbitrary number and kind of read ports
 
 - LUT RAM (aka distributed RAM): uses LUT storage as RAM
-  
+
   - Supported on most FPGAs (with notable exception of ice40)
   - Usually has one synchronous write port, one or more asynchronous read ports
   - Small
@@ -141,7 +141,7 @@ to four memory primitive classes available for selection:
 - Huge RAM:
 
   - Only supported on several targets:
-    
+
     - Some Xilinx UltraScale devices (UltraRAM)
 
       - Two ports, both with mutually exclusive synchronous read and write
@@ -154,7 +154,7 @@ to four memory primitive classes available for selection:
       - Does not support initial data
 
     - Nexus (large RAM)
-      
+
       - Two ports, both with mutually exclusive synchronous read and write
       - Single clock
 
@@ -304,7 +304,7 @@ Synchronous SDP with undefined collision behavior
 
 		if (read_enable) begin
 			read_data <= mem[read_addr];
-		
+
 		if (write_enable && read_addr == write_addr)
 			// this if block
 			read_data <= 'x;
@@ -322,7 +322,7 @@ Synchronous SDP with undefined collision behavior
 		if (write_enable)
 			mem[write_addr] <= write_data;
 
-		if (read_enable) 
+		if (read_enable)
 			read_data <= mem[read_addr];
 	end
 
@@ -446,7 +446,7 @@ Synchronous single-port RAM with write-first behavior
 		if (read_enable)
 			if (write_enable)
 				read_data <= write_data;
-			else 
+			else
 				read_data <= mem[addr];
 	end
 

docs/source/using_yosys/synthesis/techmap_synth.rst

@@ -1,4 +1,4 @@
-Technology mapping 
+Technology mapping
 ==================
 
 .. todo:: less academic, check text is coherent