mirrors/yosys
3
0
Fork 0
mirror of https://github.com/YosysHQ/yosys synced 2025-06-09 07:33:25 +00:00
Code Activity

Merge pull request #392 from azonenberg/greenpak-portfixes

Browse source 
Fixed bug causing GP_SPI model to not synthesize
This commit is contained in:
Clifford Wolf 2017-08-28 15:29:58 +02:00 • committed by GitHub
commit a682800187
1 changed files with 2 additions and 2 deletions
Download patch file Download diff file Expand all files Collapse all files

4
techlibs/greenpak4/cells_sim.v
View file

@ -113,8 +113,8 @@ module GP_SPI(
output reg[7:0] RXD_LOW, output reg[7:0] RXD_LOW,
output reg INT); output reg INT);
initial DOUT_HIGH = 0; initial RXD_HIGH = 0;
initial DOUT_LOW = 0; initial RXD_LOW = 0;
initial INT = 0; initial INT = 0;
parameter DATA_WIDTH = 8; //byte or word width parameter DATA_WIDTH = 8; //byte or word width