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	Progress in Verific bindings
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					 4 changed files with 15 additions and 2 deletions
				
			
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			@ -429,6 +429,8 @@ static void import_netlist(RTLIL::Design *design, Netlist *nl, std::set<Netlist*
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		import_attributes(wire->attributes, port);
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		module->add(wire);
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		wire->port_id = nl->IndexOf(port) + 1;
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		if (port->GetDir() == DIR_INOUT || port->GetDir() == DIR_IN)
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			wire->port_input = true;
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		if (port->GetDir() == DIR_INOUT || port->GetDir() == DIR_OUT)
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			@ -1,3 +1,6 @@
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// VERIFIC-SKIP
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module uut_forgen01(a, y);
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input [4:0] a;
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			@ -10,7 +10,7 @@ module MyMem #(
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  output [DataWidth-1:0] Data_o,
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  input                  WR_i);
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  reg Data_o;
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  reg [DataWidth-1:0] Data_o;
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  localparam Size = 2**AddrWidth;
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			@ -82,7 +82,7 @@ do
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	[[ "$bn" == *_tb ]] && continue
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	echo -n "Test: $bn "
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	rm -f ${bn}.{err,log}
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	rm -f ${bn}.{err,log,sikp}
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	mkdir -p ${bn}.out
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	rm -rf ${bn}.out/*
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			@ -111,6 +111,11 @@ do
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			test_count=$(( test_count + 1 ))
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		}
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		if [ "$frontend" = "verific" -o "$frontend" = "verific_gates" ] && grep -q VERIFIC-SKIP $fn; then
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			touch ../${bn}.skip
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			return
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		fi
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		if [ -n "$scriptfiles" ]; then
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			test_passes $fn $scriptfiles
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		elif [ -n "$scriptopt" ]; then
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			@ -137,6 +142,9 @@ do
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	if [ -f ${bn}.log ]; then
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		mv ${bn}.err ${bn}.log
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		echo "-> ok"
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	elif [ -f ${bn}.skip ]; then
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		mv ${bn}.err ${bn}.skip
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		echo "-> skip"
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	else echo "-> ERROR!"; $keeprunning || exit 1; fi
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done
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