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Progress in Verific bindings

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This commit is contained in:
Clifford Wolf 2014-03-17 01:56:00 +01:00
parent acda74c12c
commit a67cd2d4a2
4 changed files with 15 additions and 2 deletions
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2
tests/simple/mem_arst.v
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@ -10,7 +10,7 @@ module MyMem #(
output [DataWidth-1:0] Data_o,
input WR_i);
reg Data_o;
reg [DataWidth-1:0] Data_o;
localparam Size = 2**AddrWidth;