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Progress in Verific bindings

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This commit is contained in:
Clifford Wolf 2014-03-17 01:56:00 +01:00
parent acda74c12c
commit a67cd2d4a2
4 changed files with 15 additions and 2 deletions
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2
frontends/verific/verific.cc
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@ -429,6 +429,8 @@ static void import_netlist(RTLIL::Design *design, Netlist *nl, std::set<Netlist*
import_attributes(wire->attributes, port);
module->add(wire);
wire->port_id = nl->IndexOf(port) + 1;
if (port->GetDir() == DIR_INOUT || port->GetDir() == DIR_IN)
wire->port_input = true;
if (port->GetDir() == DIR_INOUT || port->GetDir() == DIR_OUT)