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Added TRANSPARENT parameter to $memrd (and RD_TRANSPARENT to $mem)

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Clifford Wolf 2014-02-03 13:01:45 +01:00
parent de9226a64f
commit a6750b3753
11 changed files with 186 additions and 78 deletions
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39
tests/simple/memory.v
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@ -75,3 +75,42 @@ assign y4 = mem2[addr][bit];
endmodule
// ----------------------------------------------------------
module test03(clk, wr_addr, wr_data, wr_enable, rd_addr, rd_data);
input clk, wr_enable;
input [3:0] wr_addr, wr_data, rd_addr;
output reg [3:0] rd_data;
reg [3:0] memory [0:15];
always @(posedge clk) begin
if (wr_enable)
memory[wr_addr] <= wr_data;
rd_data <= memory[rd_addr];
end
endmodule
// ----------------------------------------------------------
module test04(clk, wr_addr, wr_data, wr_enable, rd_addr, rd_data);
input clk, wr_enable;
input [3:0] wr_addr, wr_data, rd_addr;
output [3:0] rd_data;
reg rd_addr_buf;
reg [3:0] memory [0:15];
always @(posedge clk) begin
if (wr_enable)
memory[wr_addr] <= wr_data;
rd_addr_buf <= rd_addr;
end
assign rd_data = memory[rd_addr_buf];
endmodule