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verilog: fix width/sign detection for functions

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This commit is contained in:
Zachary Snow 2022-05-30 16:45:39 -04:00
parent cea7e85d60
commit a650d9079f
4 changed files with 55 additions and 5 deletions
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4
tests/verilog/func_tern_hint.ys Normal file
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@ -0,0 +1,4 @@
read_verilog -sv func_tern_hint.sv
proc
opt
sat -verify -seq 1 -prove-asserts -show-all