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verilog: fix width/sign detection for functions

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Zachary Snow 2022-05-30 16:45:39 -04:00
parent cea7e85d60
commit a650d9079f
4 changed files with 55 additions and 5 deletions
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CHANGELOG
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@ -14,6 +14,8 @@ Yosys 0.17 .. Yosys 0.17-dev
the remaining cases
- Fixed size and signedness computation for expressions containing array
querying functions
- Fixed size and signedness computation of functions used in ternary
expressions or case item expressions
Yosys 0.16 .. Yosys 0.17
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