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coolrunner2: Initial techmapping for $sop
This commit is contained in:
Robert Ou
parent
6e0fb889fa
commit
a64b56648d
4 changed files with 250 additions and 135 deletions
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@ -27,152 +27,153 @@ PRIVATE_NAMESPACE_BEGIN
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struct SynthCoolrunner2Pass : public ScriptPass
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{
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SynthCoolrunner2Pass() : ScriptPass("synth_coolrunner2", "synthesis for Xilinx Coolrunner-II CPLDs") { }
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SynthCoolrunner2Pass() : ScriptPass("synth_coolrunner2", "synthesis for Xilinx Coolrunner-II CPLDs") { }
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virtual void help() YS_OVERRIDE
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{
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// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
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log("\n");
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log(" synth_coolrunner2 [options]\n");
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log("\n");
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log("This command runs synthesis for Coolrunner-II CPLDs. This work is experimental.\n");
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log("It is intended to be used with https://github.com/azonenberg/openfpga as the\n");
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log("place-and-route.\n");
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log("\n");
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log(" -top <module>\n");
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log(" use the specified module as top module (default='top')\n");
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log("\n");
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log(" -json <file>\n");
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log(" write the design to the specified JSON file. writing of an output file\n");
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log(" is omitted if this parameter is not specified.\n");
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log("\n");
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log(" -run <from_label>:<to_label>\n");
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log(" only run the commands between the labels (see below). an empty\n");
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log(" from label is synonymous to 'begin', and empty to label is\n");
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log(" synonymous to the end of the command list.\n");
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log("\n");
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log(" -noflatten\n");
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log(" do not flatten design before synthesis\n");
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log("\n");
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log(" -retime\n");
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log(" run 'abc' with -dff option\n");
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log("\n");
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log("\n");
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log("The following commands are executed by this synthesis command:\n");
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help_script();
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log("\n");
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}
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virtual void help() YS_OVERRIDE
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{
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// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
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log("\n");
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log(" synth_coolrunner2 [options]\n");
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log("\n");
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log("This command runs synthesis for Coolrunner-II CPLDs. This work is experimental.\n");
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log("It is intended to be used with https://github.com/azonenberg/openfpga as the\n");
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log("place-and-route.\n");
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log("\n");
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log(" -top <module>\n");
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log(" use the specified module as top module (default='top')\n");
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log("\n");
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log(" -json <file>\n");
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log(" write the design to the specified JSON file. writing of an output file\n");
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log(" is omitted if this parameter is not specified.\n");
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log("\n");
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log(" -run <from_label>:<to_label>\n");
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log(" only run the commands between the labels (see below). an empty\n");
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log(" from label is synonymous to 'begin', and empty to label is\n");
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log(" synonymous to the end of the command list.\n");
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log("\n");
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log(" -noflatten\n");
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log(" do not flatten design before synthesis\n");
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log("\n");
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log(" -retime\n");
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log(" run 'abc' with -dff option\n");
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log("\n");
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log("\n");
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log("The following commands are executed by this synthesis command:\n");
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help_script();
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log("\n");
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}
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string top_opt, json_file;
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bool flatten, retime;
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string top_opt, json_file;
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bool flatten, retime;
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virtual void clear_flags() YS_OVERRIDE
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{
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top_opt = "-auto-top";
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json_file = "";
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flatten = true;
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retime = false;
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}
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virtual void clear_flags() YS_OVERRIDE
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{
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top_opt = "-auto-top";
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json_file = "";
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flatten = true;
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retime = false;
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}
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virtual void execute(std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE
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{
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string run_from, run_to;
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clear_flags();
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virtual void execute(std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE
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{
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string run_from, run_to;
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clear_flags();
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size_t argidx;
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for (argidx = 1; argidx < args.size(); argidx++)
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{
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if (args[argidx] == "-top" && argidx+1 < args.size()) {
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top_opt = "-top " + args[++argidx];
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continue;
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}
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if (args[argidx] == "-json" && argidx+1 < args.size()) {
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json_file = args[++argidx];
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continue;
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}
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if (args[argidx] == "-run" && argidx+1 < args.size()) {
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size_t pos = args[argidx+1].find(':');
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if (pos == std::string::npos)
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break;
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run_from = args[++argidx].substr(0, pos);
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run_to = args[argidx].substr(pos+1);
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continue;
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}
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if (args[argidx] == "-noflatten") {
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flatten = false;
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continue;
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}
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if (args[argidx] == "-retime") {
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retime = true;
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continue;
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}
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break;
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}
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extra_args(args, argidx, design);
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size_t argidx;
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for (argidx = 1; argidx < args.size(); argidx++)
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{
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if (args[argidx] == "-top" && argidx+1 < args.size()) {
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top_opt = "-top " + args[++argidx];
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continue;
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}
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if (args[argidx] == "-json" && argidx+1 < args.size()) {
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json_file = args[++argidx];
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continue;
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}
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if (args[argidx] == "-run" && argidx+1 < args.size()) {
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size_t pos = args[argidx+1].find(':');
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if (pos == std::string::npos)
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break;
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run_from = args[++argidx].substr(0, pos);
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run_to = args[argidx].substr(pos+1);
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continue;
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}
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if (args[argidx] == "-noflatten") {
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flatten = false;
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continue;
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}
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if (args[argidx] == "-retime") {
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retime = true;
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continue;
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}
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break;
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}
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extra_args(args, argidx, design);
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if (!design->full_selection())
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log_cmd_error("This comannd only operates on fully selected designs!\n");
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if (!design->full_selection())
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log_cmd_error("This comannd only operates on fully selected designs!\n");
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log_header(design, "Executing SYNTH_COOLRUNNER2 pass.\n");
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log_push();
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log_header(design, "Executing SYNTH_COOLRUNNER2 pass.\n");
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log_push();
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run_script(design, run_from, run_to);
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run_script(design, run_from, run_to);
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log_pop();
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}
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log_pop();
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}
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virtual void script() YS_OVERRIDE
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{
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if (check_label("begin"))
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{
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run("read_verilog -lib +/coolrunner2/cells_sim.v");
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run(stringf("hierarchy -check %s", help_mode ? "-top <top>" : top_opt.c_str()));
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}
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virtual void script() YS_OVERRIDE
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{
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if (check_label("begin"))
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{
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run("read_verilog -lib +/coolrunner2/cells_sim.v");
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run(stringf("hierarchy -check %s", help_mode ? "-top <top>" : top_opt.c_str()));
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}
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if (flatten && check_label("flatten", "(unless -noflatten)"))
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{
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run("proc");
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run("flatten");
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run("tribuf -logic");
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}
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if (flatten && check_label("flatten", "(unless -noflatten)"))
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{
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run("proc");
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run("flatten");
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run("tribuf -logic");
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}
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if (check_label("coarse"))
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{
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run("synth -run coarse");
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}
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if (check_label("coarse"))
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{
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run("synth -run coarse");
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}
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if (check_label("fine"))
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{
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run("opt -fast -full");
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run("techmap");
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}
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if (check_label("fine"))
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{
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run("opt -fast -full");
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run("techmap");
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}
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if (check_label("map_pla"))
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{
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run("abc -sop -I 40 -P 56");
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run("opt -fast");
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}
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if (check_label("map_pla"))
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{
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run("abc -sop -I 40 -P 56");
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run("coolrunner2_sop");
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run("opt -fast");
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}
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if (check_label("map_cells"))
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{
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run("iopadmap -bits -inpad IBUF O:I -outpad IOBUFE I:IO -inoutpad IOBUFE O:IO -toutpad IOBUFE E:I:IO -tinoutpad IOBUFE E:O:I:IO");
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}
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if (check_label("map_cells"))
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{
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run("iopadmap -bits -inpad IBUF O:I -outpad IOBUFE I:IO -inoutpad IOBUFE O:IO -toutpad IOBUFE E:I:IO -tinoutpad IOBUFE E:O:I:IO");
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}
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if (check_label("check"))
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{
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run("hierarchy -check");
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run("stat");
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run("check -noinit");
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}
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if (check_label("check"))
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{
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run("hierarchy -check");
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run("stat");
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run("check -noinit");
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}
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if (check_label("json"))
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{
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if (!json_file.empty() || help_mode)
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run(stringf("write_json %s", help_mode ? "<file-name>" : json_file.c_str()));
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}
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if (check_label("json"))
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{
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if (!json_file.empty() || help_mode)
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run(stringf("write_json %s", help_mode ? "<file-name>" : json_file.c_str()));
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}
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log_pop();
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}
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log_pop();
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}
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} SynthCoolrunner2Pass;
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PRIVATE_NAMESPACE_END
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