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Removed RTLIL::SigSpec::expand() method

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This commit is contained in:
Clifford Wolf 2014-07-23 16:09:27 +02:00
parent 54552f6809
commit a62c21c9c6
16 changed files with 231 additions and 429 deletions
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57
passes/techmap/extract.cc
View file

@ -130,11 +130,8 @@ namespace
RTLIL::SigSpec needleSig = conn.second;
RTLIL::SigSpec haystackSig = haystackCell->connections.at(portMapping.at(conn.first));
needleSig.expand();
haystackSig.expand();
for (int i = 0; i < std::min(needleSig.size(), haystackSig.size()); i++) {
RTLIL::Wire *needleWire = needleSig.chunks().at(i).wire, *haystackWire = haystackSig.chunks().at(i).wire;
RTLIL::Wire *needleWire = needleSig[i].wire, *haystackWire = haystackSig[i].wire;
if (needleWire != lastNeedleWire || haystackWire != lastHaystackWire)
if (!compareAttributes(wire_attr, needleWire ? needleWire->attributes : emptyAttr, haystackWire ? haystackWire->attributes : emptyAttr))
return false;
@ -156,7 +153,7 @@ namespace
int max_fanout = -1, std::set<std::pair<RTLIL::IdString, RTLIL::IdString>> *split = NULL)
{
SigMap sigmap(mod);
std::map<RTLIL::SigChunk, bit_ref_t> sig_bit_ref;
std::map<RTLIL::SigBit, bit_ref_t> sig_bit_ref;
if (sel && !sel->selected(mod)) {
log(" Skipping module %s as it is not selected.\n", id2cstr(mod->name));
@ -192,10 +189,9 @@ namespace
for (auto &conn : cell->connections) {
RTLIL::SigSpec conn_sig = conn.second;
sigmap.apply(conn_sig);
conn_sig.expand();
for (auto &chunk : conn_sig.chunks())
if (chunk.wire != NULL)
sig_use_count[std::pair<RTLIL::Wire*, int>(chunk.wire, chunk.offset)]++;
for (auto &bit : conn_sig)
if (bit.wire != NULL)
sig_use_count[std::pair<RTLIL::Wire*, int>(bit.wire, bit.offset)]++;
}
}
@ -220,39 +216,37 @@ namespace
RTLIL::SigSpec conn_sig = conn.second;
sigmap.apply(conn_sig);
conn_sig.expand();
for (size_t i = 0; i < conn_sig.chunks().size(); i++)
for (int i = 0; i < conn_sig.size(); i++)
{
auto &chunk = conn_sig.chunks()[i];
assert(chunk.width == 1);
auto &bit = conn_sig[i];
if (chunk.wire == NULL) {
if (bit.wire == NULL) {
if (constports) {
std::string node = "$const$x";
if (chunk.data.bits[0] == RTLIL::State::S0) node = "$const$0";
if (chunk.data.bits[0] == RTLIL::State::S1) node = "$const$1";
if (chunk.data.bits[0] == RTLIL::State::Sz) node = "$const$z";
if (bit == RTLIL::State::S0) node = "$const$0";
if (bit == RTLIL::State::S1) node = "$const$1";
if (bit == RTLIL::State::Sz) node = "$const$z";
graph.createConnection(cell->name, conn.first, i, node, "\\Y", 0);
} else
graph.createConstant(cell->name, conn.first, i, int(chunk.data.bits[0]));
graph.createConstant(cell->name, conn.first, i, int(bit.data));
continue;
}
if (max_fanout > 0 && sig_use_count[std::pair<RTLIL::Wire*, int>(chunk.wire, chunk.offset)] > max_fanout)
if (max_fanout > 0 && sig_use_count[std::pair<RTLIL::Wire*, int>(bit.wire, bit.offset)] > max_fanout)
continue;
if (sel && !sel->selected(mod, chunk.wire))
if (sel && !sel->selected(mod, bit.wire))
continue;
if (sig_bit_ref.count(chunk) == 0) {
bit_ref_t &bit_ref = sig_bit_ref[chunk];
if (sig_bit_ref.count(bit) == 0) {
bit_ref_t &bit_ref = sig_bit_ref[bit];
bit_ref.cell = cell->name;
bit_ref.port = conn.first;
bit_ref.bit = i;
}
bit_ref_t &bit_ref = sig_bit_ref[chunk];
bit_ref_t &bit_ref = sig_bit_ref[bit];
graph.createConnection(bit_ref.cell, bit_ref.port, bit_ref.bit, cell->name, conn.first, i);
}
}
@ -267,11 +261,10 @@ namespace
{
RTLIL::SigSpec conn_sig = conn.second;
sigmap.apply(conn_sig);
conn_sig.expand();
for (auto &chunk : conn_sig.chunks())
if (sig_bit_ref.count(chunk) != 0) {
bit_ref_t &bit_ref = sig_bit_ref[chunk];
for (auto &bit : conn_sig)
if (sig_bit_ref.count(bit) != 0) {
bit_ref_t &bit_ref = sig_bit_ref[bit];
graph.markExtern(bit_ref.cell, bit_ref.port, bit_ref.bit);
}
}
@ -285,11 +278,10 @@ namespace
{
RTLIL::SigSpec conn_sig(wire);
sigmap.apply(conn_sig);
conn_sig.expand();
for (auto &chunk : conn_sig.chunks())
if (sig_bit_ref.count(chunk) != 0) {
bit_ref_t &bit_ref = sig_bit_ref[chunk];
for (auto &bit : conn_sig)
if (sig_bit_ref.count(bit) != 0) {
bit_ref_t &bit_ref = sig_bit_ref[bit];
graph.markExtern(bit_ref.cell, bit_ref.port, bit_ref.bit);
}
}
@ -333,9 +325,8 @@ namespace
for (auto &conn : needle_cell->connections) {
RTLIL::SigSpec sig = sigmap(conn.second);
if (mapping.portMapping.count(conn.first) > 0 && sig2port.has(sigmap(sig))) {
sig.expand();
for (int i = 0; i < sig.size(); i++)
for (auto &port : sig2port.find(sig.chunks()[i])) {
for (auto &port : sig2port.find(sig[i])) {
RTLIL::SigSpec bitsig = haystack_cell->connections.at(mapping.portMapping[conn.first]).extract(i, 1);
cell->connections.at(port.first).replace(port.second, bitsig);
}

143
passes/techmap/simplemap.cc
View file

@ -29,75 +29,60 @@ extern void simplemap_get_mappers(std::map<std::string, void(*)(RTLIL::Module*,
static void simplemap_not(RTLIL::Module *module, RTLIL::Cell *cell)
{
int width = cell->parameters.at("\\Y_WIDTH").as_int();
RTLIL::SigSpec sig_a = cell->connections.at("\\A");
sig_a.extend(width, cell->parameters.at("\\A_SIGNED").as_bool());
sig_a.expand();
RTLIL::SigSpec sig_y = cell->connections.at("\\Y");
sig_y.expand();
for (int i = 0; i < width; i++) {
sig_a.extend(SIZE(sig_y), cell->parameters.at("\\A_SIGNED").as_bool());
for (int i = 0; i < SIZE(sig_y); i++) {
RTLIL::Cell *gate = new RTLIL::Cell;
gate->name = NEW_ID;
gate->type = "$_INV_";
gate->connections["\\A"] = sig_a.chunks().at(i);
gate->connections["\\Y"] = sig_y.chunks().at(i);
gate->connections["\\A"] = sig_a[i];
gate->connections["\\Y"] = sig_y[i];
module->add(gate);
}
}
static void simplemap_pos(RTLIL::Module *module, RTLIL::Cell *cell)
{
int width = cell->parameters.at("\\Y_WIDTH").as_int();
RTLIL::SigSpec sig_a = cell->connections.at("\\A");
sig_a.extend(width, cell->parameters.at("\\A_SIGNED").as_bool());
RTLIL::SigSpec sig_y = cell->connections.at("\\Y");
sig_a.extend(SIZE(sig_y), cell->parameters.at("\\A_SIGNED").as_bool());
module->connections.push_back(RTLIL::SigSig(sig_y, sig_a));
}
static void simplemap_bu0(RTLIL::Module *module, RTLIL::Cell *cell)
{
int width = cell->parameters.at("\\Y_WIDTH").as_int();
RTLIL::SigSpec sig_a = cell->connections.at("\\A");
sig_a.extend_u0(width, cell->parameters.at("\\A_SIGNED").as_bool());
RTLIL::SigSpec sig_y = cell->connections.at("\\Y");
sig_a.extend_u0(SIZE(sig_y), cell->parameters.at("\\A_SIGNED").as_bool());
module->connections.push_back(RTLIL::SigSig(sig_y, sig_a));
}
static void simplemap_bitop(RTLIL::Module *module, RTLIL::Cell *cell)
{
int width = cell->parameters.at("\\Y_WIDTH").as_int();
RTLIL::SigSpec sig_a = cell->connections.at("\\A");
sig_a.extend_u0(width, cell->parameters.at("\\A_SIGNED").as_bool());
sig_a.expand();
RTLIL::SigSpec sig_b = cell->connections.at("\\B");
sig_b.extend_u0(width, cell->parameters.at("\\B_SIGNED").as_bool());
sig_b.expand();
RTLIL::SigSpec sig_y = cell->connections.at("\\Y");
sig_y.expand();
sig_a.extend_u0(SIZE(sig_y), cell->parameters.at("\\A_SIGNED").as_bool());
sig_b.extend_u0(SIZE(sig_y), cell->parameters.at("\\B_SIGNED").as_bool());
if (cell->type == "$xnor")
{
RTLIL::SigSpec sig_t = module->addWire(NEW_ID, width);
sig_t.expand();
RTLIL::SigSpec sig_t = module->addWire(NEW_ID, SIZE(sig_y));
for (int i = 0; i < width; i++) {
for (int i = 0; i < SIZE(sig_y); i++) {
RTLIL::Cell *gate = new RTLIL::Cell;
gate->name = NEW_ID;
gate->type = "$_INV_";
gate->connections["\\A"] = sig_t.chunks().at(i);
gate->connections["\\Y"] = sig_y.chunks().at(i);
gate->connections["\\A"] = sig_t[i];
gate->connections["\\Y"] = sig_y[i];
module->add(gate);
}
@ -111,13 +96,13 @@ static void simplemap_bitop(RTLIL::Module *module, RTLIL::Cell *cell)
if (cell->type == "$xnor") gate_type = "$_XOR_";
log_assert(!gate_type.empty());
for (int i = 0; i < width; i++) {
for (int i = 0; i < SIZE(sig_y); i++) {
RTLIL::Cell *gate = new RTLIL::Cell;
gate->name = NEW_ID;
gate->type = gate_type;
gate->connections["\\A"] = sig_a.chunks().at(i);
gate->connections["\\B"] = sig_b.chunks().at(i);
gate->connections["\\Y"] = sig_y.chunks().at(i);
gate->connections["\\A"] = sig_a[i];
gate->connections["\\B"] = sig_b[i];
gate->connections["\\Y"] = sig_y[i];
module->add(gate);
}
}
@ -125,8 +110,6 @@ static void simplemap_bitop(RTLIL::Module *module, RTLIL::Cell *cell)
static void simplemap_reduce(RTLIL::Module *module, RTLIL::Cell *cell)
{
RTLIL::SigSpec sig_a = cell->connections.at("\\A");
sig_a.expand();
RTLIL::SigSpec sig_y = cell->connections.at("\\Y");
if (sig_y.size() == 0)
@ -159,21 +142,20 @@ static void simplemap_reduce(RTLIL::Module *module, RTLIL::Cell *cell)
while (sig_a.size() > 1)
{
RTLIL::SigSpec sig_t = module->addWire(NEW_ID, sig_a.size() / 2);
sig_t.expand();
for (int i = 0; i < sig_a.size(); i += 2)
{
if (i+1 == sig_a.size()) {
sig_t.append(sig_a.chunks().at(i));
sig_t.append(sig_a[i]);
continue;
}
RTLIL::Cell *gate = new RTLIL::Cell;
gate->name = NEW_ID;
gate->type = gate_type;
gate->connections["\\A"] = sig_a.chunks().at(i);
gate->connections["\\B"] = sig_a.chunks().at(i+1);
gate->connections["\\Y"] = sig_t.chunks().at(i/2);
gate->connections["\\A"] = sig_a[i];
gate->connections["\\B"] = sig_a[i+1];
gate->connections["\\Y"] = sig_t[i/2];
last_output = &gate->connections["\\Y"];
module->add(gate);
}
@ -202,26 +184,23 @@ static void simplemap_reduce(RTLIL::Module *module, RTLIL::Cell *cell)
static void logic_reduce(RTLIL::Module *module, RTLIL::SigSpec &sig)
{
sig.expand();
while (sig.size() > 1)
{
RTLIL::SigSpec sig_t = module->addWire(NEW_ID, sig.size() / 2);
sig_t.expand();
for (int i = 0; i < sig.size(); i += 2)
{
if (i+1 == sig.size()) {
sig_t.append(sig.chunks().at(i));
sig_t.append(sig[i]);
continue;
}
RTLIL::Cell *gate = new RTLIL::Cell;
gate->name = NEW_ID;
gate->type = "$_OR_";
gate->connections["\\A"] = sig.chunks().at(i);
gate->connections["\\B"] = sig.chunks().at(i+1);
gate->connections["\\Y"] = sig_t.chunks().at(i/2);
gate->connections["\\A"] = sig[i];
gate->connections["\\B"] = sig[i+1];
gate->connections["\\Y"] = sig_t[i/2];
module->add(gate);
}
@ -289,25 +268,18 @@ static void simplemap_logbin(RTLIL::Module *module, RTLIL::Cell *cell)
static void simplemap_mux(RTLIL::Module *module, RTLIL::Cell *cell)
{
int width = cell->parameters.at("\\WIDTH").as_int();
RTLIL::SigSpec sig_a = cell->connections.at("\\A");
sig_a.expand();
RTLIL::SigSpec sig_b = cell->connections.at("\\B");
sig_b.expand();
RTLIL::SigSpec sig_y = cell->connections.at("\\Y");
sig_y.expand();
for (int i = 0; i < width; i++) {
for (int i = 0; i < SIZE(sig_y); i++) {
RTLIL::Cell *gate = new RTLIL::Cell;
gate->name = NEW_ID;
gate->type = "$_MUX_";
gate->connections["\\A"] = sig_a.chunks().at(i);
gate->connections["\\B"] = sig_b.chunks().at(i);
gate->connections["\\A"] = sig_a[i];
gate->connections["\\B"] = sig_b[i];
gate->connections["\\S"] = cell->connections.at("\\S");
gate->connections["\\Y"] = sig_y.chunks().at(i);
gate->connections["\\Y"] = sig_y[i];
module->add(gate);
}
}
@ -335,13 +307,8 @@ static void simplemap_sr(RTLIL::Module *module, RTLIL::Cell *cell)
char clr_pol = cell->parameters.at("\\CLR_POLARITY").as_bool() ? 'P' : 'N';
RTLIL::SigSpec sig_s = cell->connections.at("\\SET");
sig_s.expand();
RTLIL::SigSpec sig_r = cell->connections.at("\\CLR");
sig_r.expand();
RTLIL::SigSpec sig_q = cell->connections.at("\\Q");
sig_q.expand();
std::string gate_type = stringf("$_SR_%c%c_", set_pol, clr_pol);
@ -349,9 +316,9 @@ static void simplemap_sr(RTLIL::Module *module, RTLIL::Cell *cell)
RTLIL::Cell *gate = new RTLIL::Cell;
gate->name = NEW_ID;
gate->type = gate_type;
gate->connections["\\S"] = sig_s.chunks().at(i);
gate->connections["\\R"] = sig_r.chunks().at(i);
gate->connections["\\Q"] = sig_q.chunks().at(i);
gate->connections["\\S"] = sig_s[i];
gate->connections["\\R"] = sig_r[i];
gate->connections["\\Q"] = sig_q[i];
module->add(gate);
}
}
@ -362,12 +329,8 @@ static void simplemap_dff(RTLIL::Module *module, RTLIL::Cell *cell)
char clk_pol = cell->parameters.at("\\CLK_POLARITY").as_bool() ? 'P' : 'N';
RTLIL::SigSpec sig_clk = cell->connections.at("\\CLK");
RTLIL::SigSpec sig_d = cell->connections.at("\\D");
sig_d.expand();
RTLIL::SigSpec sig_q = cell->connections.at("\\Q");
sig_q.expand();
std::string gate_type = stringf("$_DFF_%c_", clk_pol);
@ -376,8 +339,8 @@ static void simplemap_dff(RTLIL::Module *module, RTLIL::Cell *cell)
gate->name = NEW_ID;
gate->type = gate_type;
gate->connections["\\C"] = sig_clk;
gate->connections["\\D"] = sig_d.chunks().at(i);
gate->connections["\\Q"] = sig_q.chunks().at(i);
gate->connections["\\D"] = sig_d[i];
gate->connections["\\Q"] = sig_q[i];
module->add(gate);
}
}
@ -390,18 +353,10 @@ static void simplemap_dffsr(RTLIL::Module *module, RTLIL::Cell *cell)
char clr_pol = cell->parameters.at("\\CLR_POLARITY").as_bool() ? 'P' : 'N';
RTLIL::SigSpec sig_clk = cell->connections.at("\\CLK");
RTLIL::SigSpec sig_s = cell->connections.at("\\SET");
sig_s.expand();
RTLIL::SigSpec sig_r = cell->connections.at("\\CLR");
sig_r.expand();
RTLIL::SigSpec sig_d = cell->connections.at("\\D");
sig_d.expand();
RTLIL::SigSpec sig_q = cell->connections.at("\\Q");
sig_q.expand();
std::string gate_type = stringf("$_DFFSR_%c%c%c_", clk_pol, set_pol, clr_pol);
@ -410,10 +365,10 @@ static void simplemap_dffsr(RTLIL::Module *module, RTLIL::Cell *cell)
gate->name = NEW_ID;
gate->type = gate_type;
gate->connections["\\C"] = sig_clk;
gate->connections["\\S"] = sig_s.chunks().at(i);
gate->connections["\\R"] = sig_r.chunks().at(i);
gate->connections["\\D"] = sig_d.chunks().at(i);
gate->connections["\\Q"] = sig_q.chunks().at(i);
gate->connections["\\S"] = sig_s[i];
gate->connections["\\R"] = sig_r[i];
gate->connections["\\D"] = sig_d[i];
gate->connections["\\Q"] = sig_q[i];
module->add(gate);
}
}
@ -430,12 +385,8 @@ static void simplemap_adff(RTLIL::Module *module, RTLIL::Cell *cell)
RTLIL::SigSpec sig_clk = cell->connections.at("\\CLK");
RTLIL::SigSpec sig_rst = cell->connections.at("\\ARST");
RTLIL::SigSpec sig_d = cell->connections.at("\\D");
sig_d.expand();
RTLIL::SigSpec sig_q = cell->connections.at("\\Q");
sig_q.expand();
std::string gate_type_0 = stringf("$_DFF_%c%c0_", clk_pol, rst_pol);
std::string gate_type_1 = stringf("$_DFF_%c%c1_", clk_pol, rst_pol);
@ -446,8 +397,8 @@ static void simplemap_adff(RTLIL::Module *module, RTLIL::Cell *cell)
gate->type = rst_val.at(i) == RTLIL::State::S1 ? gate_type_1 : gate_type_0;
gate->connections["\\C"] = sig_clk;
gate->connections["\\R"] = sig_rst;
gate->connections["\\D"] = sig_d.chunks().at(i);
gate->connections["\\Q"] = sig_q.chunks().at(i);
gate->connections["\\D"] = sig_d[i];
gate->connections["\\Q"] = sig_q[i];
module->add(gate);
}
}
@ -458,12 +409,8 @@ static void simplemap_dlatch(RTLIL::Module *module, RTLIL::Cell *cell)
char en_pol = cell->parameters.at("\\EN_POLARITY").as_bool() ? 'P' : 'N';
RTLIL::SigSpec sig_en = cell->connections.at("\\EN");
RTLIL::SigSpec sig_d = cell->connections.at("\\D");
sig_d.expand();
RTLIL::SigSpec sig_q = cell->connections.at("\\Q");
sig_q.expand();
std::string gate_type = stringf("$_DLATCH_%c_", en_pol);
@ -472,8 +419,8 @@ static void simplemap_dlatch(RTLIL::Module *module, RTLIL::Cell *cell)
gate->name = NEW_ID;
gate->type = gate_type;
gate->connections["\\E"] = sig_en;
gate->connections["\\D"] = sig_d.chunks().at(i);
gate->connections["\\Q"] = sig_q.chunks().at(i);
gate->connections["\\D"] = sig_d[i];
gate->connections["\\Q"] = sig_q[i];
module->add(gate);
}
}