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Removed RTLIL::SigSpec::expand() method
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parent
54552f6809
commit
a62c21c9c6
16 changed files with 231 additions and 429 deletions
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@ -21,7 +21,7 @@ static void find_stub_nets(RTLIL::Design *design, RTLIL::Module *module, bool re
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SigMap sigmap(module);
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// count how many times a single-bit signal is used
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std::map<RTLIL::SigSpec, int> bit_usage_count;
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std::map<RTLIL::SigBit, int> bit_usage_count;
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// count ouput lines for this module (needed only for summary output at the end)
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int line_count = 0;
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@ -36,13 +36,10 @@ static void find_stub_nets(RTLIL::Design *design, RTLIL::Module *module, bool re
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// (use sigmap to get a uniqe signal name)
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RTLIL::SigSpec sig = sigmap(conn.second);
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// split the signal up into single-bit chunks
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sig.expand();
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// add each chunk to bit_usage_count, unless it is a constant
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for (auto &c : sig.chunks)
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if (c.wire != NULL)
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bit_usage_count[c]++;
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// add each bit to bit_usage_count, unless it is a constant
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for (auto &bit : sig)
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if (bit.wire != NULL)
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bit_usage_count[bit]++;
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}
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// for each wire in the module
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@ -62,13 +59,11 @@ static void find_stub_nets(RTLIL::Design *design, RTLIL::Module *module, bool re
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// get a signal description for this wire and split it into seperate bits
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RTLIL::SigSpec sig = sigmap(wire);
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sig.expand();
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// for each bit (unless it is a constant):
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// check if it is used at least two times and add to stub_bits otherwise
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for (size_t i = 0; i < sig.chunks.size(); i++)
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if (sig.chunks[i].wire != NULL && (bit_usage_count[sig.chunks[i]] +
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usage_offset) < 2)
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for (size_t i = 0; i < SIZE(sig); i++)
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if (sig[i].wire != NULL && (bit_usage_count[sig[i]] + usage_offset) < 2)
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stub_bits.insert(i);
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// continue if no stub bits found
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