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ast, read_verilog: refactoring

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This commit is contained in:
Emil J. Tywoniak 2025-06-18 12:39:32 +02:00
parent 51fc94cf2d
commit a6293df781
7 changed files with 16 additions and 21 deletions
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2
frontends/ast/genrtlil.cc
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@ -1339,8 +1339,6 @@ RTLIL::SigSpec AstNode::genRTLIL(int width_hint, bool sign_hint)
// be instantiated for this type of AST node.
IdString type_name;
current_filename = filename;
switch (type)
{
// simply ignore this nodes.

4
frontends/ast/simplify.cc
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@ -1038,8 +1038,6 @@ bool AstNode::simplify(bool const_fold, int stage, int width_hint, bool sign_hin
return false;
}
current_filename = filename;
// we do not look inside a task or function
// (but as soon as a task or function is instantiated we process the generated AST as usual)
if (type == AST_FUNCTION || type == AST_TASK) {
@ -1906,8 +1904,6 @@ bool AstNode::simplify(bool const_fold, int stage, int width_hint, bool sign_hin
current_scope[it->first] = it->second;
}
current_filename = filename;
if (type == AST_MODULE || type == AST_INTERFACE)
current_scope.clear();