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Added help command to README (and some other README changes)

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Clifford Wolf 2013-02-28 14:17:57 +01:00
parent af561800ed
commit a5c4bf2161
1 changed files with 14 additions and 12 deletions
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README
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@ -23,15 +23,14 @@
yosys -- Yosys Open SYnthesis Suite yosys -- Yosys Open SYnthesis Suite
=================================== ===================================
This is a framework for RTL synthesis tools. It is highly This is a framework for RTL synthesis tools. It currently has
experimental and under construction. The goal for now is extensive Verilog-2005 support and provides a basic set of
to implement an extensible Verilog-2005 synthesis tool. synthesis algorithms for various application domains.
The aim of this tool is to generate valid logic netlists Yosys can be adapted to perform any synthesis job by combining
from HDL designs in a manner that allows for easy addition the existing passes (algorithms) using synthesis scripts and
of extra synthesis passes. This tool does not aim at generating adding additional passes as needed by extending the yosys c++
efficient logic netlists. This can be done by passing the codebase.
output of Yosys to a low-level synthesis tool such as ABC.
Yosys is free software licensed under the ISC license (a GPL Yosys is free software licensed under the ISC license (a GPL
compatible licence that is similar in terms to the MIT license compatible licence that is similar in terms to the MIT license
@ -59,6 +58,11 @@ a simple synthesis job using the interactive command shell:
$ ./yosys $ ./yosys
yosys> yosys>
the command "help" can be used to pritn a list of all available
commands and "help <command>" to print details on the specified command:
yosys> help help
reading the design using the verilog frontend: reading the design using the verilog frontend:
yosys> read_verilog tests/simple/fiedler-cooley.v yosys> read_verilog tests/simple/fiedler-cooley.v
@ -127,7 +131,7 @@ synthesis script will synthesize for the given cell library:
hierarchy; proc; memory; opt; fsm; opt hierarchy; proc; memory; opt; fsm; opt
# mapping to internal cell library # mapping to internal cell library
techmap techmap; opt
# mapping flip-flops to mycells.lib # mapping flip-flops to mycells.lib
dfflibmap -liberty mycells.lib dfflibmap -liberty mycells.lib
@ -213,13 +217,11 @@ TODOs / Open Bugs
- Additional internal cell types: $pla and $lut - Additional internal cell types: $pla and $lut
- Subsystem for selecting stuff (and limiting scope of passes)
- Support for registering designs (as collection of modules) to CellTypes - Support for registering designs (as collection of modules) to CellTypes
- Kernel support for collections of cells (from input/output cones, etc) - Kernel support for collections of cells (from input/output cones, etc)
- Smarter resource sharing pass (add MUXes and get rid of duplicated cells) - Smarter resource sharing pass (add MUXes and get rid of duplicated cells)
- Better FSM state encoding and technology mapping - Better FSM state encoding