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Sign-extension related fixes in SatGen and AST frontend

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This commit is contained in:
Clifford Wolf 2013-06-10 17:10:06 +02:00
parent 9026511821
commit a5c30183b5
2 changed files with 10 additions and 8 deletions
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2
frontends/ast/genrtlil.cc
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@ -768,6 +768,8 @@ RTLIL::SigSpec AstNode::genRTLIL(int width_hint)
int width = std::max(left.width, right.width); int width = std::max(left.width, right.width);
if (width > width_hint && width_hint > 0) if (width > width_hint && width_hint > 0)
width = width_hint; width = width_hint;
if (width < width_hint)
width = width_hint;
return binop2rtlil(this, type_name, width, left, right); return binop2rtlil(this, type_name, width, left, right);
} }

16
kernel/satgen.h
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@ -76,15 +76,13 @@ struct SatGen
void extendSignalWidth(std::vector<int> &vec_a, std::vector<int> &vec_b, RTLIL::Cell *cell, size_t y_width = 0) void extendSignalWidth(std::vector<int> &vec_a, std::vector<int> &vec_b, RTLIL::Cell *cell, size_t y_width = 0)
{ {
bool is_signed_a = false, is_signed_b = false; bool is_signed = false;
if (cell->parameters.count("\\A_SIGNED") > 0) if (cell->parameters.count("\\A_SIGNED") > 0 && cell->parameters.count("\\B_SIGNED") > 0)
is_signed_a = cell->parameters["\\A_SIGNED"].as_bool(); is_signed = cell->parameters["\\A_SIGNED"].as_bool() && cell->parameters["\\B_SIGNED"].as_bool();
if (cell->parameters.count("\\B_SIGNED") > 0)
is_signed_b = cell->parameters["\\B_SIGNED"].as_bool();
while (vec_a.size() < vec_b.size() || vec_a.size() < y_width) while (vec_a.size() < vec_b.size() || vec_a.size() < y_width)
vec_a.push_back(is_signed_a && vec_a.size() > 0 ? vec_a.back() : ez->FALSE); vec_a.push_back(is_signed && vec_a.size() > 0 ? vec_a.back() : ez->FALSE);
while (vec_b.size() < vec_a.size() || vec_b.size() < y_width) while (vec_b.size() < vec_a.size() || vec_b.size() < y_width)
vec_b.push_back(is_signed_b && vec_b.size() > 0 ? vec_b.back() : ez->FALSE); vec_b.push_back(is_signed && vec_b.size() > 0 ? vec_b.back() : ez->FALSE);
} }
void extendSignalWidth(std::vector<int> &vec_a, std::vector<int> &vec_b, std::vector<int> &vec_y, RTLIL::Cell *cell) void extendSignalWidth(std::vector<int> &vec_a, std::vector<int> &vec_b, std::vector<int> &vec_y, RTLIL::Cell *cell)
@ -222,9 +220,11 @@ struct SatGen
std::vector<int> b = importSigSpec(cell->connections.at("\\B"), timestep); std::vector<int> b = importSigSpec(cell->connections.at("\\B"), timestep);
std::vector<int> y = importSigSpec(cell->connections.at("\\Y"), timestep); std::vector<int> y = importSigSpec(cell->connections.at("\\Y"), timestep);
char shift_left = cell->type == "$shl" || cell->type == "$sshl"; char shift_left = cell->type == "$shl" || cell->type == "$sshl";
bool sign_extend = cell->type == "$sshr"; bool sign_extend = cell->type == "$sshr" && cell->parameters["\\A_SIGNED"].as_bool();
while (y.size() < a.size()) while (y.size() < a.size())
y.push_back(ez->literal()); y.push_back(ez->literal());
while (y.size() > a.size())
a.push_back(cell->parameters["\\A_SIGNED"].as_bool() ? a.back() : ez->FALSE);
std::vector<int> tmp = a; std::vector<int> tmp = a;
for (size_t i = 0; i < b.size(); i++) for (size_t i = 0; i < b.size(); i++)
{ {