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Fix warnings

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This commit is contained in:
Eddie Hung 2019-12-31 18:40:11 -08:00
parent c082329af3
commit a59016b146
2 changed files with 2 additions and 2 deletions
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2
tests/arch/ice40/mul.ys
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@ -1,6 +1,6 @@
read_verilog ../common/mul.v
hierarchy -top top
equiv_opt -assert -map +/ice40/cells_sim.v synth_ice40 -dsp # equivalency check
equiv_opt -assert -multiclock -map +/ice40/cells_sim.v synth_ice40 -dsp # equivalency check
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
cd top # Constrain all select calls below inside the top module
select -assert-count 1 t:SB_MAC16