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Compute is_port in AbcPass without iterating through all cells and wires in the module every time we run ABC.

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This does not scale when we run ABC thousands of times in a single AbcPass.
This commit is contained in:
Robert O'Callahan 2025-07-27 23:44:41 +00:00
parent d3b0c0df1a
commit a54a673586
5 changed files with 264 additions and 91 deletions
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kernel/ffmerge.h
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@ -58,7 +58,7 @@ YOSYS_NAMESPACE_BEGIN
struct FfMergeHelper
{
const SigMap *sigmap;
const SigMapView *sigmap;
RTLIL::Module *module;
FfInitVals *initvals;