From a519390fc41ff07c3eba54386528b85c6be5a4f6 Mon Sep 17 00:00:00 2001 From: garytwong Date: Thu, 19 Jun 2025 16:41:18 +0000 Subject: [PATCH] verilog: fix string literal regular expression (#5187) * verilog: fix string literal regular expression. A backslash was improperly quoted, causing string literal matching to fail when the final token before a closing quote was an escaped backslash. * verilog: add regression test for string literal regex bug. Test for bug triggered by escaped backslash immediately before closing quote (introduced in ca7d94af and fixed by 40aa7eaf). --- frontends/verilog/verilog_lexer.l | 2 +- tests/verilog/bug5160.v | 5 +++++ 2 files changed, 6 insertions(+), 1 deletion(-) create mode 100644 tests/verilog/bug5160.v diff --git a/frontends/verilog/verilog_lexer.l b/frontends/verilog/verilog_lexer.l index 8e6e022b1..be9a439b0 100644 --- a/frontends/verilog/verilog_lexer.l +++ b/frontends/verilog/verilog_lexer.l @@ -371,7 +371,7 @@ TIME_SCALE_SUFFIX [munpf]?s } \" { BEGIN(STRING); } -([^\"]|\\.)+ { yymore(); } +([^\\"]|\\.)+ { yymore(); } \" { BEGIN(0); char *yystr = strdup(YYText()); diff --git a/tests/verilog/bug5160.v b/tests/verilog/bug5160.v new file mode 100644 index 000000000..5b141a360 --- /dev/null +++ b/tests/verilog/bug5160.v @@ -0,0 +1,5 @@ +// Regression test for bug mentioned in #5160: +// https://github.com/YosysHQ/yosys/pull/5160#issuecomment-2983643084 +module top; + initial $display( "\\" ); +endmodule