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	Documentation updates
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							|  | @ -245,7 +245,6 @@ TODOs / Open Bugs | |||
|   - Indexed part selects | ||||
|   - Multi-dimensional arrays | ||||
|   - ROM modeling using "initial" blocks | ||||
|   - The "defparam <cell_name>.<parameter_name> = <value>;" syntax | ||||
|   - Built-in primitive gates (and, nand, cmos, nmos, pmos, etc..) | ||||
|   - Ignore what needs to be ignored (e.g. drive and charge strengths) | ||||
|   - Check standard vs. implementation to identify missing features | ||||
|  | @ -255,11 +254,9 @@ TODOs / Open Bugs | |||
|   - Actually use range information on parameters | ||||
|   - Add brief source code documentation to most passes and kernel code | ||||
|   - Implement mux-to-tribuf pass and rebalance mixed mux/tribuf trees | ||||
|   - Add 'edit' command for changing the design (delete, add, modify objects) | ||||
|   - Improve TCL support and add 'list' command for inspecting the design from TCL | ||||
|   - Add edit commands for changing the design (delete, add, modify objects) | ||||
|   - Improve TCL support (add mechanism for inspecting the design from TCL) | ||||
|   - Additional internal cell types: $pla and $lut | ||||
|   - Support for registering designs (as collection of modules) to CellTypes | ||||
|   - Smarter resource sharing pass (add MUXes and get rid of duplicated cells) | ||||
|   - For pass' "fsm_detect" help: add notes what criteria lets it detect an FSM | ||||
|   - Better FSM state encoding | ||||
| 
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|  |  | |||
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