mirror of
				https://github.com/YosysHQ/yosys
				synced 2025-10-31 11:42:30 +00:00 
			
		
		
		
	Documentation updates
This commit is contained in:
		
							parent
							
								
									56432a920f
								
							
						
					
					
						commit
						a4fd3cde8c
					
				
					 1 changed files with 2 additions and 5 deletions
				
			
		
							
								
								
									
										7
									
								
								README
									
										
									
									
									
								
							
							
						
						
									
										7
									
								
								README
									
										
									
									
									
								
							|  | @ -245,7 +245,6 @@ TODOs / Open Bugs | ||||||
|   - Indexed part selects |   - Indexed part selects | ||||||
|   - Multi-dimensional arrays |   - Multi-dimensional arrays | ||||||
|   - ROM modeling using "initial" blocks |   - ROM modeling using "initial" blocks | ||||||
|   - The "defparam <cell_name>.<parameter_name> = <value>;" syntax |  | ||||||
|   - Built-in primitive gates (and, nand, cmos, nmos, pmos, etc..) |   - Built-in primitive gates (and, nand, cmos, nmos, pmos, etc..) | ||||||
|   - Ignore what needs to be ignored (e.g. drive and charge strengths) |   - Ignore what needs to be ignored (e.g. drive and charge strengths) | ||||||
|   - Check standard vs. implementation to identify missing features |   - Check standard vs. implementation to identify missing features | ||||||
|  | @ -255,11 +254,9 @@ TODOs / Open Bugs | ||||||
|   - Actually use range information on parameters |   - Actually use range information on parameters | ||||||
|   - Add brief source code documentation to most passes and kernel code |   - Add brief source code documentation to most passes and kernel code | ||||||
|   - Implement mux-to-tribuf pass and rebalance mixed mux/tribuf trees |   - Implement mux-to-tribuf pass and rebalance mixed mux/tribuf trees | ||||||
|   - Add 'edit' command for changing the design (delete, add, modify objects) |   - Add edit commands for changing the design (delete, add, modify objects) | ||||||
|   - Improve TCL support and add 'list' command for inspecting the design from TCL |   - Improve TCL support (add mechanism for inspecting the design from TCL) | ||||||
|   - Additional internal cell types: $pla and $lut |   - Additional internal cell types: $pla and $lut | ||||||
|   - Support for registering designs (as collection of modules) to CellTypes |   - Support for registering designs (as collection of modules) to CellTypes | ||||||
|   - Smarter resource sharing pass (add MUXes and get rid of duplicated cells) |   - Smarter resource sharing pass (add MUXes and get rid of duplicated cells) | ||||||
|   - For pass' "fsm_detect" help: add notes what criteria lets it detect an FSM |  | ||||||
|   - Better FSM state encoding |  | ||||||
| 
 | 
 | ||||||
|  |  | ||||||
		Loading…
	
	Add table
		Add a link
		
	
		Reference in a new issue