mirrors/yosys
3
0
Fork 0
mirror of https://github.com/YosysHQ/yosys synced 2026-02-14 21:01:50 +00:00
Code Activity

Merge 5a613fc457 into b890b1b43f

Browse source
This commit is contained in:
Emil J 2026-02-11 09:03:13 -08:00 • committed by GitHub
commit a4b29b4179
No known key found for this signature in database
GPG key ID: B5690EEEBB952194
24 changed files with 641 additions and 107 deletions
Download patch file Download diff file Expand all files Collapse all files

32
techlibs/common/simlib.v
View file

@ -3250,3 +3250,35 @@ parameter WIDTH = 0;
inout [WIDTH-1:0] Y;
endmodule
// --------------------------------------------------------
//-
//- $priority (A, Y)
//* group unary
//-
//- Priority operator. An output bit is set if the input bit at the same index is set and no lower index input bit is set.
//-
module \$priority (A, Y);
parameter WIDTH = 0;
parameter POLARITY = 0;
input [WIDTH-1:0] A;
output [WIDTH-1:0] Y;
wire [WIDTH-1:0] tmp;
wire [WIDTH-1:0] A_active;
wire [WIDTH-1:0] Y_active;
assign A_active = A ^ ~POLARITY;
assign Y = Y_active ^ ~POLARITY;
genvar i;
generate
if (WIDTH > 0) begin
assign tmp[0] = A_active[0];
assign Y_active[0] = A_active[0];
end
for (i = 1; i < WIDTH; i = i + 1) begin
assign Y_active[i] = tmp[i-1] ? 1'b0 : A_active[i];
assign tmp[i] = tmp[i-1] | A_active[i];
end
endgenerate
endmodule

33
techlibs/common/techmap.v
View file

@ -679,3 +679,36 @@ parameter WIDTH = 0;
inout [WIDTH-1:0] Y; // This cell is just a maker, so we leave Y undriven
endmodule
(* techmap_celltype = "$priority" *)
module \$priority (A, Y);
parameter WIDTH = 0;
parameter POLARITY = 0;
(* force_downto *)
input [WIDTH-1:0] A;
(* force_downto *)
output [WIDTH-1:0] Y;
(* force_downto *)
wire [WIDTH-1:0] tmp;
(* force_downto *)
wire [WIDTH-1:0] A_active;
(* force_downto *)
wire [WIDTH-1:0] Y_active;
assign A_active = A ^ ~POLARITY;
assign Y = Y_active ^ ~POLARITY;
genvar i;
generate
if (WIDTH > 0) begin
assign tmp[0] = A_active[0];
assign Y_active[0] = A_active[0];
end
for (i = 1; i < WIDTH; i = i + 1) begin
assign Y_active[i] = tmp[i-1] ? 1'b0 : A_active[i];
assign tmp[i] = tmp[i-1] | A_active[i];
end
endgenerate
endmodule