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https://github.com/YosysHQ/yosys
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Merge pull request #54 from alaindargelas/obs_clean
Observability clean pass
This commit is contained in:
Akash Levy
GitHub
commit
a49e492693
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@ -5,6 +5,7 @@ OBJS += passes/silimate/annotate_logic_depth.o
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OBJS += passes/silimate/breaksop.o
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OBJS += passes/silimate/bus_rebuild.o
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OBJS += passes/silimate/longloop_select.o
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OBJS += passes/silimate/obs_clean.o
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OBJS += passes/silimate/opt_balance_tree.o
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OBJS += passes/silimate/segv.o
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OBJS += passes/silimate/selectconst.o
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273
passes/silimate/obs_clean.cc
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273
passes/silimate/obs_clean.cc
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@ -0,0 +1,273 @@
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#include "kernel/sigtools.h"
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#include "kernel/yosys.h"
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#include <set>
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USING_YOSYS_NAMESPACE
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PRIVATE_NAMESPACE_BEGIN
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// Signal cell driver(s), precompute a cell output signal to a cell map
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void sigCellDrivers(RTLIL::Module *module, SigMap &sigmap, dict<RTLIL::SigSpec, std::set<Cell *>> &sig2CellsInFanout,
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dict<RTLIL::SigSpec, std::set<Cell *>> &sig2CellsInFanin)
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{
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for (auto cell : module->selected_cells()) {
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for (auto &conn : cell->connections()) {
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IdString portName = conn.first;
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RTLIL::SigSpec actual = conn.second;
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if (cell->output(portName)) {
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sig2CellsInFanin[sigmap(actual)].insert(cell);
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for (int i = 0; i < actual.size(); i++) {
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SigSpec bit_sig = actual.extract(i, 1);
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sig2CellsInFanin[sigmap(bit_sig)].insert(cell);
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}
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} else {
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sig2CellsInFanout[sigmap(actual)].insert(cell);
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for (int i = 0; i < actual.size(); i++) {
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SigSpec bit_sig = actual.extract(i, 1);
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if (!bit_sig.is_fully_const()) {
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sig2CellsInFanout[sigmap(bit_sig)].insert(cell);
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}
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}
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}
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}
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}
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}
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// Assign statements fanin, fanout, traces the lhs2rhs and rhs2lhs sigspecs and precompute maps
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void lhs2rhs_rhs2lhs(RTLIL::Module *module, SigMap &sigmap, dict<RTLIL::SigSpec, std::set<RTLIL::SigSpec>> &rhsSig2LhsSig,
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dict<RTLIL::SigSpec, RTLIL::SigSpec> &lhsSig2rhsSig)
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{
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for (auto it = module->connections().begin(); it != module->connections().end(); ++it) {
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RTLIL::SigSpec lhs = it->first;
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RTLIL::SigSpec rhs = it->second;
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if (!lhs.is_chunk()) {
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std::vector<SigSpec> lhsBits;
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for (int i = 0; i < lhs.size(); i++) {
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SigSpec bit_sig = lhs.extract(i, 1);
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lhsBits.push_back(bit_sig);
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}
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std::vector<SigSpec> rhsBits;
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for (int i = 0; i < rhs.size(); i++) {
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SigSpec bit_sig = rhs.extract(i, 1);
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rhsBits.push_back(bit_sig);
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}
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for (uint32_t i = 0; i < lhsBits.size(); i++) {
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if (i < rhsBits.size()) {
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rhsSig2LhsSig[sigmap(rhsBits[i])].insert(sigmap(lhsBits[i]));
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lhsSig2rhsSig[lhsBits[i]] = sigmap(rhsBits[i]);
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}
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}
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} else {
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rhsSig2LhsSig[sigmap(rhs)].insert(sigmap(lhs));
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lhsSig2rhsSig[lhs] = sigmap(rhs);
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}
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}
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}
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// Collect transitive fanin of a sig
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void collectTransitiveFanin(RTLIL::SigSpec &sig, SigMap &sigmap, dict<RTLIL::SigSpec, std::set<Cell *>> &sig2CellsInFanin,
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dict<RTLIL::SigSpec, RTLIL::SigSpec> &lhsSig2RhsSig, std::set<Cell *> &visitedCells,
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std::set<RTLIL::SigSpec> &visitedSigSpec)
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{
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if (visitedSigSpec.count(sigmap(sig))) {
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return;
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}
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visitedSigSpec.insert(sigmap(sig));
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if (sig2CellsInFanin.count(sigmap(sig))) {
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for (Cell *cell : sig2CellsInFanin[sigmap(sig)]) {
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if (visitedCells.count(cell)) {
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continue;
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}
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visitedCells.insert(cell);
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for (auto &conn : cell->connections()) {
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IdString portName = conn.first;
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RTLIL::SigSpec actual = conn.second;
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if (cell->input(portName)) {
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collectTransitiveFanin(actual, sigmap, sig2CellsInFanin, lhsSig2RhsSig, visitedCells, visitedSigSpec);
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for (int i = 0; i < actual.size(); i++) {
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SigSpec bit_sig = actual.extract(i, 1);
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collectTransitiveFanin(bit_sig, sigmap, sig2CellsInFanin, lhsSig2RhsSig, visitedCells,
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visitedSigSpec);
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}
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}
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}
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}
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}
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if (lhsSig2RhsSig.count(sigmap(sig))) {
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RTLIL::SigSpec rhs = lhsSig2RhsSig[sigmap(sig)];
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collectTransitiveFanin(rhs, sigmap, sig2CellsInFanin, lhsSig2RhsSig, visitedCells, visitedSigSpec);
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for (int i = 0; i < rhs.size(); i++) {
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SigSpec bit_sig = rhs.extract(i, 1);
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collectTransitiveFanin(bit_sig, sigmap, sig2CellsInFanin, lhsSig2RhsSig, visitedCells, visitedSigSpec);
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}
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}
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}
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// Only keep the cells and wires that are visited using the transitive fanin reached from output ports or keep signals
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void observabilityClean(RTLIL::Module *module, SigMap &sigmap, dict<RTLIL::SigSpec, std::set<Cell *>> &sig2CellsInFanin,
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dict<RTLIL::SigSpec, RTLIL::SigSpec> &lhsSig2RhsSig, bool unused_wires)
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{
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if (module->get_bool_attribute(ID::keep))
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return;
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std::set<Cell *> visitedCells;
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std::set<RTLIL::SigSpec> visitedSigSpec;
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// Collect observable logic (connected to one output)
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for (auto elt : sig2CellsInFanin) {
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RTLIL::SigSpec po = elt.first;
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RTLIL::Wire *w = po[0].wire;
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if (w && (!w->port_output) && (!w->get_bool_attribute(ID::keep))) {
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continue;
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}
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RTLIL::SigSpec spo = sigmap(po);
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collectTransitiveFanin(spo, sigmap, sig2CellsInFanin, lhsSig2RhsSig, visitedCells, visitedSigSpec);
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for (int i = 0; i < po.size(); i++) {
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SigSpec bit_sig = po.extract(i, 1);
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bit_sig = sigmap(bit_sig);
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collectTransitiveFanin(bit_sig, sigmap, sig2CellsInFanin, lhsSig2RhsSig, visitedCells, visitedSigSpec);
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}
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}
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for (auto elt : lhsSig2RhsSig) {
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RTLIL::SigSpec po = elt.first;
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RTLIL::Wire *w = po[0].wire;
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if (w && (!w->port_output) && (!w->get_bool_attribute(ID::keep))) {
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continue;
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}
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RTLIL::SigSpec spo = sigmap(po);
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collectTransitiveFanin(spo, sigmap, sig2CellsInFanin, lhsSig2RhsSig, visitedCells, visitedSigSpec);
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for (int i = 0; i < po.size(); i++) {
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SigSpec bit_sig = po.extract(i, 1);
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bit_sig = sigmap(bit_sig);
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collectTransitiveFanin(bit_sig, sigmap, sig2CellsInFanin, lhsSig2RhsSig, visitedCells, visitedSigSpec);
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}
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}
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// Remove unused assign stmts
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std::vector<RTLIL::SigSig> newConnections;
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for (auto it = module->connections().begin(); it != module->connections().end(); ++it) {
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RTLIL::SigSpec lhs = it->first;
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if (visitedSigSpec.count(sigmap(lhs))) {
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newConnections.push_back(*it);
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} else {
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for (int i = 0; i < lhs.size(); i++) {
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SigSpec bit_sig = lhs.extract(i, 1);
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if (visitedSigSpec.count(sigmap(bit_sig))) {
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newConnections.push_back(*it);
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break;
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}
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}
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}
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}
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module->connections_.clear();
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for (auto conn : newConnections) {
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module->connect(conn);
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}
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if (unused_wires) {
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// Remove unused wires
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// TODO: This impacts equiv_opt ability to perform equivalence checking
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pool<RTLIL::Wire *> wiresToRemove;
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for (auto wire : module->wires()) {
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RTLIL::SigSpec sig = wire;
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if (visitedSigSpec.count(sigmap(sig))) {
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continue;
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}
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bool bitVisited = false;
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for (int i = 0; i < sig.size(); i++) {
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SigSpec bit_sig = sig.extract(i, 1);
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if (visitedSigSpec.count(bit_sig)) {
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bitVisited = true;
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break;
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}
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}
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if (bitVisited)
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continue;
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if (wire->port_id) {
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continue;
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}
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if (wire->get_bool_attribute(ID::keep))
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continue;
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wiresToRemove.insert(wire);
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}
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module->remove(wiresToRemove);
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}
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// Remove unused cells
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std::set<Cell *> cellsToRemove;
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for (auto cell : module->cells()) {
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if (visitedCells.count(cell)) {
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continue;
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}
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if (cell->has_keep_attr())
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continue;
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cellsToRemove.insert(cell);
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}
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for (auto cell : cellsToRemove) {
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module->remove(cell);
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}
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}
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struct ObsClean : public ScriptPass {
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ObsClean() : ScriptPass("obs_clean", "Observability-based cleanup") {}
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void script() override {}
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void help() override
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{
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log("\n");
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log(" obs_clean [options] [selection]\n");
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log("\n");
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log("This pass performs an obversability-based logic removal.\n");
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log("\n");
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log(" -wires\n");
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log(" Also removes dangling wires. This option prevents formal verifciation at this time.\n");
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log("\n");
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}
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void execute(std::vector<std::string> args, RTLIL::Design *design) override
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{
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bool unused_wires = false;
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size_t argidx;
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for (argidx = 1; argidx < args.size(); argidx++) {
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if (args[argidx] == "-wires") {
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unused_wires = true;
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continue;
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}
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break;
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}
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extra_args(args, argidx, design);
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if (design == nullptr) {
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log_error("No design object");
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return;
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}
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log("Running obs_clean pass\n");
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log_flush();
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for (auto module : design->selected_modules()) {
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// We cannot safely perform this analysis when processes or memories are present
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if (module->has_processes_warn())
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continue;
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if (module->has_memories_warn())
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continue;
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SigMap sigmap(module);
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// Precompute cell output sigspec to cell map
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dict<RTLIL::SigSpec, std::set<Cell *>> sig2CellsInFanin;
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dict<RTLIL::SigSpec, std::set<Cell *>> sig2CellsInFanout;
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sigCellDrivers(module, sigmap, sig2CellsInFanout, sig2CellsInFanin);
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// Precompute lhs2rhs and rhs2lhs sigspec map
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dict<RTLIL::SigSpec, RTLIL::SigSpec> lhsSig2RhsSig;
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dict<RTLIL::SigSpec, std::set<RTLIL::SigSpec>> rhsSig2LhsSig;
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lhs2rhs_rhs2lhs(module, sigmap, rhsSig2LhsSig, lhsSig2RhsSig);
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// Actual cleanup
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observabilityClean(module, sigmap, sig2CellsInFanin, lhsSig2RhsSig, unused_wires);
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}
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log("End obs_clean pass\n");
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log_flush();
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}
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} SplitNetlist;
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PRIVATE_NAMESPACE_END
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