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put back previous test state, due to default change

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This commit is contained in:
Miodrag Milanovic 2023-08-29 10:21:58 +02:00
parent 792cf8326e
commit a42c630264
3 changed files with 6 additions and 6 deletions
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2
tests/arch/machxo2/lutram.ys
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@ -2,7 +2,7 @@ read_verilog ../common/lutram.v
hierarchy -top lutram_1w1r
proc
memory -nomap
equiv_opt -run :prove -map +/lattice/cells_sim_xo2.v synth_lattice -family xo2 -nowidelut
equiv_opt -run :prove -map +/lattice/cells_sim_xo2.v synth_lattice -family xo2
memory
opt -full