mirrors/yosys
3
0
Fork 0
mirror of https://github.com/YosysHQ/yosys synced 2025-10-30 19:22:31 +00:00
Code Activity

Revert "Remove _TECHMAP_CELLTYPE_ check since all $mul"

Browse source 
This reverts commit 234738b103.
This commit is contained in:
Eddie Hung 2019-09-25 17:25:44 -07:00
parent f4387e817c
commit a4238637ac
1 changed files with 6 additions and 2 deletions
Download patch file Download diff file Expand all files Collapse all files

8
techlibs/common/mul2dsp.v
View file

@ -61,6 +61,8 @@ module _80_mul (A, B, Y);
input [B_WIDTH-1:0] B; input [B_WIDTH-1:0] B;
output [Y_WIDTH-1:0] Y; output [Y_WIDTH-1:0] Y;
parameter _TECHMAP_CELLTYPE_ = "";
generate generate
if (0) begin end if (0) begin end
`ifdef DSP_A_MINWIDTH `ifdef DSP_A_MINWIDTH
@ -75,8 +77,10 @@ module _80_mul (A, B, Y);
else if (Y_WIDTH < `DSP_Y_MINWIDTH) else if (Y_WIDTH < `DSP_Y_MINWIDTH)
wire _TECHMAP_FAIL_ = 1; wire _TECHMAP_FAIL_ = 1;
`endif `endif
else if (_TECHMAP_CELLTYPE_ == "$mul" && A_SIGNED != B_SIGNED)
wire _TECHMAP_FAIL_ = 1;
`ifdef DSP_SIGNEDONLY `ifdef DSP_SIGNEDONLY
else if (!A_SIGNED) else if (_TECHMAP_CELLTYPE_ == "$mul" && !A_SIGNED)
\$mul #( \$mul #(
.A_SIGNED(1), .A_SIGNED(1),
.B_SIGNED(1), .B_SIGNED(1),
@ -89,7 +93,7 @@ module _80_mul (A, B, Y);
.Y(Y) .Y(Y)
); );
`endif `endif
else if (A_WIDTH < B_WIDTH) else if (_TECHMAP_CELLTYPE_ == "$mul" && A_WIDTH < B_WIDTH)
\$mul #( \$mul #(
.A_SIGNED(B_SIGNED), .A_SIGNED(B_SIGNED),
.B_SIGNED(A_SIGNED), .B_SIGNED(A_SIGNED),