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qbfsat: Use bit precise mapping for hole value wires and a more robust hole spec for writing to and specializing from a solution file.

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This commit is contained in:
Alberto Gonzalez 2020-05-22 04:48:33 +00:00
parent 992d694d39
commit a3d1f8637a
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GPG key ID: 8395A8BA109708B2
2 changed files with 120 additions and 79 deletions
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8
kernel/rtlil.h
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@ -754,6 +754,7 @@ struct RTLIL::SigBit
SigBit(const RTLIL::SigBit &sigbit) = default;
RTLIL::SigBit &operator =(const RTLIL::SigBit &other) = default;
std::string str() const;
bool operator <(const RTLIL::SigBit &other) const;
bool operator ==(const RTLIL::SigBit &other) const;
bool operator !=(const RTLIL::SigBit &other) const;
@ -1547,6 +1548,13 @@ inline RTLIL::SigBit::SigBit(RTLIL::Wire *wire, int offset) : wire(wire), offset
inline RTLIL::SigBit::SigBit(const RTLIL::SigChunk &chunk) : wire(chunk.wire) { log_assert(chunk.width == 1); if (wire) offset = chunk.offset; else data = chunk.data[0]; }
inline RTLIL::SigBit::SigBit(const RTLIL::SigChunk &chunk, int index) : wire(chunk.wire) { if (wire) offset = chunk.offset + index; else data = chunk.data[index]; }
inline std::string RTLIL::SigBit::str() const {
if (wire != nullptr)
return stringf("%s[%d]", wire->name.c_str(), offset);
else
return stringf("%u", data);
}
inline bool RTLIL::SigBit::operator<(const RTLIL::SigBit &other) const {
if (wire == other.wire)
return wire ? (offset < other.offset) : (data < other.data);