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Fix TRELLIS_FF simulation model

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Miodrag Milanovic 2019-08-31 11:12:06 +02:00
parent 90b44113d8
commit a3c16a0565
1 changed files with 7 additions and 6 deletions
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13
techlibs/ecp5/cells_sim.v
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@ -229,14 +229,15 @@ module TRELLIS_FF(input CLK, LSR, CE, DI, M, output reg Q);
parameter REGSET = "RESET";
parameter [127:0] LSRMODE = "LSR";
reg muxce;
always @(*)
wire muxce;
generate
case (CEMUX)
"1": muxce = 1'b1;
"0": muxce = 1'b0;
"INV": muxce = ~CE;
default: muxce = CE;
"1": assign muxce = 1'b1;
"0": assign muxce = 1'b0;
"INV": assign muxce = ~CE;
default: assign muxce = CE;
endcase
endgenerate
wire muxlsr = (LSRMUX == "INV") ? ~LSR : LSR;
wire muxclk = (CLKMUX == "INV") ? ~CLK : CLK;