diff --git a/frontends/blif/blifparse.cc b/frontends/blif/blifparse.cc
index 65d53ab98..8d851c3c4 100644
--- a/frontends/blif/blifparse.cc
+++ b/frontends/blif/blifparse.cc
@@ -362,19 +362,19 @@ void parse_blif(RTLIL::Design *design, std::istream &f, IdString dff_name, bool
 					goto no_latch_clock;
 
 				if (!strcmp(edge, "re"))
-					cell = module->addDff(NEW_ABC_ID, blif_wire(clock), blif_wire(d), blif_wire(q));
+					cell = module->addDff(NEW_ID, blif_wire(clock), blif_wire(d), blif_wire(q));
 				else if (!strcmp(edge, "fe"))
-					cell = module->addDff(NEW_ABC_ID, blif_wire(clock), blif_wire(d), blif_wire(q), false);
+					cell = module->addDff(NEW_ID, blif_wire(clock), blif_wire(d), blif_wire(q), false);
 				else if (!strcmp(edge, "ah"))
-					cell = module->addDlatch(NEW_ABC_ID, blif_wire(clock), blif_wire(d), blif_wire(q));
+					cell = module->addDlatch(NEW_ID, blif_wire(clock), blif_wire(d), blif_wire(q));
 				else if (!strcmp(edge, "al"))
-					cell = module->addDlatch(NEW_ABC_ID, blif_wire(clock), blif_wire(d), blif_wire(q), false);
+					cell = module->addDlatch(NEW_ID, blif_wire(clock), blif_wire(d), blif_wire(q), false);
 				else {
 			no_latch_clock:
 					if (dff_name.empty()) {
-						cell = module->addFf(NEW_ABC_ID, blif_wire(d), blif_wire(q));
+						cell = module->addFf(NEW_ID, blif_wire(d), blif_wire(q));
 					} else {
-						cell = module->addCell(NEW_ABC_ID, dff_name);
+						cell = module->addCell(NEW_ID, dff_name);
 						cell->setPort(ID::D, blif_wire(d));
 						cell->setPort(ID::Q, blif_wire(q));
 					}
@@ -393,7 +393,7 @@ void parse_blif(RTLIL::Design *design, std::istream &f, IdString dff_name, bool
 					goto error;
 
 				IdString celltype = RTLIL::escape_id(p);
-				RTLIL::Cell *cell = module->addCell(NEW_ABC_ID, celltype);
+				RTLIL::Cell *cell = module->addCell(NEW_ID, celltype);
 				RTLIL::Module *cell_mod = design->module(celltype);
 
 				dict<RTLIL::IdString, dict<int, SigBit>> cell_wideports_cache;
@@ -440,7 +440,7 @@ void parse_blif(RTLIL::Design *design, std::istream &f, IdString dff_name, bool
 						if (it.second.count(idx))
 							sig.append(it.second.at(idx));
 						else
-							sig.append(module->addWire(NEW_ABC_ID));
+							sig.append(module->addWire(NEW_ID));
 					}
 
 					cell->setPort(it.first, sig);
@@ -516,7 +516,7 @@ void parse_blif(RTLIL::Design *design, std::istream &f, IdString dff_name, bool
 
 				if (sop_mode)
 				{
-					sopcell = module->addCell(NEW_ABC_ID, ID($sop));
+					sopcell = module->addCell(NEW_ID, ID($sop));
 					sopcell->parameters[ID::WIDTH] = RTLIL::Const(input_sig.size());
 					sopcell->parameters[ID::DEPTH] = 0;
 					sopcell->parameters[ID::TABLE] = RTLIL::Const();
@@ -532,7 +532,7 @@ void parse_blif(RTLIL::Design *design, std::istream &f, IdString dff_name, bool
 				}
 				else
 				{
-					RTLIL::Cell *cell = module->addCell(NEW_ABC_ID, ID($lut));
+					RTLIL::Cell *cell = module->addCell(NEW_ID, ID($lut));
 					cell->parameters[ID::WIDTH] = RTLIL::Const(input_sig.size());
 					cell->parameters[ID::LUT] = RTLIL::Const(RTLIL::State::Sx, 1 << input_sig.size());
 					cell->setPort(ID::A, input_sig);
@@ -583,8 +583,8 @@ void parse_blif(RTLIL::Design *design, std::istream &f, IdString dff_name, bool
 				sopmode = (*output == '1');
 				if (!sopmode) {
 					SigSpec outnet = sopcell->getPort(ID::Y);
-					SigSpec tempnet = module->addWire(NEW_ABC_ID);
-					module->addNotGate(NEW_ABC_ID, tempnet, outnet);
+					SigSpec tempnet = module->addWire(NEW_ID);
+					module->addNotGate(NEW_ID, tempnet, outnet);
 					sopcell->setPort(ID::Y, tempnet);
 				}
 			} else
@@ -666,4 +666,3 @@ struct BlifFrontend : public Frontend {
 } BlifFrontend;
 
 YOSYS_NAMESPACE_END
-
diff --git a/passes/opt/opt_dff.cc b/passes/opt/opt_dff.cc
index fc0637bda..2f7d0c0c3 100644
--- a/passes/opt/opt_dff.cc
+++ b/passes/opt/opt_dff.cc
@@ -395,7 +395,6 @@ struct OptDffWorker
 					// Always-active enable.  Make a comb circuit, nuke the FF/latch.
 					log("Handling always-active async load on %s (%s) from module %s (changing to combinatorial circuit).\n",
 							log_id(cell), log_id(cell->type), log_id(module));
-					ff.remove();
 					if (ff.has_sr) {
 						SigSpec tmp;
 						if (ff.is_fine) {
@@ -432,6 +431,7 @@ struct OptDffWorker
 					} else {
 						module->connect(ff.sig_q, ff.sig_ad);
 					}
+					ff.remove();
 					did_something = true;
 					continue;
 				} else if (ff.sig_ad.is_fully_const() && !ff.has_arst && !ff.has_sr) {