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quicklogic: Add basic k6n10f tests

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Martin Povišer 2023-11-27 12:14:48 +01:00
parent 90f427c7a8
commit a3b3333eeb
11 changed files with 211 additions and 0 deletions
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34
tests/arch/quicklogic/qlf_k6n10f/latches.ys Normal file
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read_verilog ../../common/latches.v
design -save read
hierarchy -top latchp
proc
# Can't run any sort of equivalence check because latches are blown to LUTs
synth_quicklogic -family qlf_k6n10f
cd latchp # Constrain all select calls below inside the top module
select -assert-count 1 t:latchsre
select -assert-none t:latchsre %% t:* %D
design -load read
hierarchy -top latchn
proc
# Can't run any sort of equivalence check because latches are blown to LUTs
synth_quicklogic -family qlf_k6n10f
cd latchn # Constrain all select calls below inside the top module
select -assert-count 1 t:latchnsre
select -assert-none t:latchnsre %% t:* %D
design -load read
hierarchy -top latchsr
proc
# Can't run any sort of equivalence check because latches are blown to LUTs
synth_quicklogic -family qlf_k6n10f
cd latchsr # Constrain all select calls below inside the top module
select -assert-count 2 t:$lut
select -assert-count 1 t:dffsr
select -assert-none t:$lut t:dffsr %% t:* %D