mirrors/yosys
3
0
Fork 0
mirror of https://github.com/YosysHQ/yosys synced 2025-10-31 03:32:29 +00:00
Code Activity

Revert "intel_alm: direct M10K instantiation"

Browse source 
This reverts commit 09ecb9b2cf.
This commit is contained in:
Lofty 2020-07-13 14:08:52 +01:00 • committed by Marcelina Kościelnicka
parent 38b814b525
commit a3a90f6377
8 changed files with 38 additions and 128 deletions
Download patch file Download diff file Expand all files Collapse all files

6
techlibs/intel_alm/Makefile.inc
View file

@ -15,9 +15,9 @@ $(eval $(call add_share_file,share/intel_alm/common,techlibs/intel_alm/common/ds
$(eval $(call add_share_file,share/intel_alm/common,techlibs/intel_alm/common/mem_sim.v)) $(eval $(call add_share_file,share/intel_alm/common,techlibs/intel_alm/common/mem_sim.v))
# RAM # RAM
$(eval $(call add_share_file,share/intel_alm/common,techlibs/intel_alm/common/bram_m10k.txt)) bramtypes := m10k m20k
$(eval $(call add_share_file,share/intel_alm/common,techlibs/intel_alm/common/bram_m20k.txt)) $(foreach bramtype, $(bramtypes), $(eval $(call add_share_file,share/intel_alm/common,techlibs/intel_alm/common/bram_$(bramtype).txt)))
$(eval $(call add_share_file,share/intel_alm/common,techlibs/intel_alm/common/bram_m20k_map.v)) $(foreach bramtype, $(bramtypes), $(eval $(call add_share_file,share/intel_alm/common,techlibs/intel_alm/common/bram_$(bramtype)_map.v)))
$(eval $(call add_share_file,share/intel_alm/common,techlibs/intel_alm/common/lutram_mlab.txt)) $(eval $(call add_share_file,share/intel_alm/common,techlibs/intel_alm/common/lutram_mlab.txt))
# Miscellaneous # Miscellaneous

4
techlibs/intel_alm/common/bram_m10k.txt
View file

@ -1,4 +1,4 @@
bram MISTRAL_M10K bram __MISTRAL_M10K_SDP
init 0 # TODO: Re-enable when I figure out how BRAM init works init 0 # TODO: Re-enable when I figure out how BRAM init works
abits 13 @D8192x1 abits 13 @D8192x1
dbits 1 @D8192x1 dbits 1 @D8192x1
@ -27,7 +27,7 @@ bram MISTRAL_M10K
endbram endbram
match MISTRAL_M10K match __MISTRAL_M10K_SDP
min efficiency 5 min efficiency 5
make_transp make_transp
endmatch endmatch

31
techlibs/intel_alm/common/bram_m10k_map.v Normal file
View file

@ -0,0 +1,31 @@
module __MISTRAL_M10K_SDP(CLK1, A1ADDR, A1DATA, A1EN, B1ADDR, B1DATA, B1EN);
parameter CFG_ABITS = 10;
parameter CFG_DBITS = 10;
parameter CFG_ENABLE_A = 1;
parameter CFG_ENABLE_B = 1;
input CLK1;
input [CFG_ABITS-1:0] A1ADDR, B1ADDR;
input [CFG_DBITS-1:0] A1DATA;
output [CFG_DBITS-1:0] B1DATA;
input [CFG_ENABLE_A-1:0] A1EN, B1EN;
altsyncram #(
.operation_mode("dual_port"),
.ram_block_type("m10k"),
.widthad_a(CFG_ABITS),
.width_a(CFG_DBITS),
.widthad_b(CFG_ABITS),
.width_b(CFG_DBITS),
) _TECHMAP_REPLACE_ (
.address_a(A1ADDR),
.data_a(A1DATA),
.wren_a(A1EN),
.address_b(B1ADDR),
.q_b(B1DATA),
.clock0(CLK1),
.clock1(CLK1)
);
endmodule

35
techlibs/intel_alm/common/megafunction_bb.v
View file

@ -157,38 +157,3 @@ input [ay_scan_in_width-1:0] ay;
output [result_a_width-1:0] resulta; output [result_a_width-1:0] resulta;
endmodule endmodule
(* blackbox *)
module cyclonev_ram_block(portaaddr, portadatain, portawe, portbaddr, portbdataout, portbre, clk0);
parameter operation_mode = "dual_port";
parameter logical_ram_name = "";
parameter port_a_address_width = 10;
parameter port_a_data_width = 10;
parameter port_a_logical_ram_depth = 1024;
parameter port_a_logical_ram_width = 10;
parameter port_a_first_address = 0;
parameter port_a_last_address = 1023;
parameter port_a_first_bit_number = 0;
parameter port_b_address_width = 10;
parameter port_b_data_width = 10;
parameter port_b_logical_ram_depth = 1024;
parameter port_b_logical_ram_width = 10;
parameter port_b_first_address = 0;
parameter port_b_last_address = 1023;
parameter port_b_first_bit_number = 0;
parameter port_b_address_clock = "clock0";
parameter port_b_read_enable_clock = "clock0";
parameter mem_init0 = "";
parameter mem_init1 = "";
parameter mem_init2 = "";
parameter mem_init3 = "";
parameter mem_init4 = "";
input [port_a_address_width-1:0] portaaddr;
input [port_b_address_width-1:0] portbaddr;
input [port_a_data_width-1:0] portadatain;
output [port_b_data_width-1:0] portbdataout;
input clk0, portawe, portbre;
endmodule

34
techlibs/intel_alm/common/mem_sim.v
View file

@ -68,37 +68,3 @@ always @(posedge CLK1)
assign B1DATA = mem[B1ADDR]; assign B1DATA = mem[B1ADDR];
endmodule endmodule
// The M10K
// --------
// TODO
module MISTRAL_M10K(CLK1, A1ADDR, A1DATA, A1EN, B1ADDR, B1DATA, B1EN);
parameter CFG_ABITS = 10;
parameter CFG_DBITS = 10;
input CLK1;
input [CFG_ABITS-1:0] A1ADDR, B1ADDR;
input [CFG_DBITS-1:0] A1DATA;
input A1EN, B1EN;
output reg [CFG_DBITS-1:0] B1DATA;
reg [2**CFG_ABITS * CFG_DBITS - 1 : 0] mem = 0;
specify
$setup(A1ADDR, posedge CLK1, 0);
$setup(A1DATA, posedge CLK1, 0);
if (B1EN) (posedge CLK1 => (B1DATA : A1DATA)) = 0;
endspecify
always @(posedge CLK1) begin
if (A1EN)
mem[(A1ADDR + 1) * CFG_DBITS - 1 : A1ADDR * CFG_DBITS] <= A1DATA;
if (B1EN)
B1DATA <= mem[(B1ADDR + 1) * CFG_DBITS - 1 : B1ADDR * CFG_DBITS];
end
endmodule

45
techlibs/intel_alm/common/quartus_rename.v
View file

@ -123,51 +123,6 @@ module MISTRAL_MLAB(input [4:0] A1ADDR, input A1DATA, A1EN, CLK1, input [4:0] B1
endmodule endmodule
module MISTRAL_M10K(A1ADDR, A1DATA, A1EN, CLK1, B1ADDR, B1DATA, B1EN);
parameter CFG_ABITS = 10;
parameter CFG_DBITS = 10;
input [CFG_ABITS-1:0] A1ADDR, B1ADDR;
input [CFG_DBITS-1:0] A1DATA;
input CLK1, A1EN, B1EN;
output [CFG_DBITS-1:0] B1DATA;
// Much like the MLAB, the M10K has mem_init[01234] parameters which would let
// you initialise the RAM cell via hex literals. If they were implemented.
cyclonev_ram_block #(
.operation_mode("dual_port"),
.logical_ram_name("MISTRAL_M10K"),
.port_a_address_width(CFG_ABITS),
.port_a_data_width(CFG_DBITS),
.port_a_logical_ram_depth(2**CFG_ABITS),
.port_a_logical_ram_width(CFG_DBITS),
.port_a_first_address(0),
.port_a_last_address(2**CFG_DBITS - 1),
.port_a_first_bit_number(0),
.port_b_address_width(CFG_ABITS),
.port_b_data_width(CFG_DBITS),
.port_b_logical_ram_depth(2**CFG_ABITS),
.port_b_logical_ram_width(CFG_DBITS),
.port_b_first_address(0),
.port_b_last_address(2**CFG_DBITS - 1),
.port_b_first_bit_number(0),
.port_b_address_clock("clock0"),
.port_b_read_enable_clock("clock0")
) _TECHMAP_REPLACE_ (
.portaaddr(A1ADDR),
.portadatain(A1DATA),
.portawe(A1EN),
.portbaddr(B1ADDR),
.portbdataout(B1DATA),
.portbre(B1EN),
.clk0(CLK1)
);
endmodule
module MISTRAL_MUL27X27(input [26:0] A, B, output [53:0] Y); module MISTRAL_MUL27X27(input [26:0] A, B, output [53:0] Y);
`MAC #(.ax_width(27), .ay_scan_in_width(27), .result_a_width(54), .operation_mode("M27x27")) _TECHMAP_REPLACE_ (.ax(A), .ay(B), .resulta(Y)); `MAC #(.ax_width(27), .ay_scan_in_width(27), .result_a_width(54), .operation_mode("M27x27")) _TECHMAP_REPLACE_ (.ax(A), .ay(B), .resulta(Y));

3
techlibs/intel_alm/synth_intel_alm.cc
View file

@ -235,8 +235,7 @@ struct SynthIntelALMPass : public ScriptPass {
if (!nobram && check_label("map_bram", "(skip if -nobram)")) { if (!nobram && check_label("map_bram", "(skip if -nobram)")) {
run(stringf("memory_bram -rules +/intel_alm/common/bram_%s.txt", bram_type.c_str())); run(stringf("memory_bram -rules +/intel_alm/common/bram_%s.txt", bram_type.c_str()));
if (help_mode || bram_type != "m10k") run(stringf("techmap -map +/intel_alm/common/bram_%s_map.v", bram_type.c_str()));
run(stringf("techmap -map +/intel_alm/common/bram_%s_map.v", bram_type.c_str()));
} }
if (!nolutram && check_label("map_lutram", "(skip if -nolutram)")) { if (!nolutram && check_label("map_lutram", "(skip if -nolutram)")) {

6
tests/arch/intel_alm/blockram.ys
View file

@ -1,6 +0,0 @@
read_verilog ../common/blockram.v
chparam -set ADDRESS_WIDTH 10 -set DATA_WIDTH 10 sync_ram_sdp
synth_intel_alm -family cyclonev
cd sync_ram_sdp
select -assert-count 1 t:MISTRAL_M10K
select -assert-none t:MISTRAL_M10K %% t:* %D