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Merge pull request #1452 from nakengelhardt/fix_dsp_mem_reg

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Call memory_dff before DSP mapping to reserve registers (fixes #1447)
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Clifford Wolf 2019-10-22 17:36:54 +02:00 committed by GitHub
parent 5025aab8c9 3b405d985e
commit a3a7bb9bf7
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GPG key ID: 4AEE18F83AFDEB23
2 changed files with 2 additions and 0 deletions
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1
techlibs/ice40/synth_ice40.cc
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@ -273,6 +273,7 @@ struct SynthIce40Pass : public ScriptPass
run("opt_expr"); run("opt_expr");
run("opt_clean"); run("opt_clean");
if (help_mode || dsp) { if (help_mode || dsp) {
run("memory_dff");
run("techmap -map +/mul2dsp.v -map +/ice40/dsp_map.v -D DSP_A_MAXWIDTH=16 -D DSP_B_MAXWIDTH=16 " run("techmap -map +/mul2dsp.v -map +/ice40/dsp_map.v -D DSP_A_MAXWIDTH=16 -D DSP_B_MAXWIDTH=16 "
"-D DSP_A_MINWIDTH=2 -D DSP_B_MINWIDTH=2 -D DSP_Y_MINWIDTH=11 " "-D DSP_A_MINWIDTH=2 -D DSP_B_MINWIDTH=2 -D DSP_Y_MINWIDTH=11 "
"-D DSP_NAME=$__MUL16X16", "(if -dsp)"); "-D DSP_NAME=$__MUL16X16", "(if -dsp)");

1
techlibs/xilinx/synth_xilinx.cc
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@ -341,6 +341,7 @@ struct SynthXilinxPass : public ScriptPass
if (check_label("map_dsp", "(skip if '-nodsp')")) { if (check_label("map_dsp", "(skip if '-nodsp')")) {
if (!nodsp || help_mode) { if (!nodsp || help_mode) {
run("memory_dff"); // xilinx_dsp will merge registers, reserve memory port registers first
// NB: Xilinx multipliers are signed only // NB: Xilinx multipliers are signed only
run("techmap -map +/mul2dsp.v -map +/xilinx/dsp_map.v -D DSP_A_MAXWIDTH=25 " run("techmap -map +/mul2dsp.v -map +/xilinx/dsp_map.v -D DSP_A_MAXWIDTH=25 "
"-D DSP_A_MAXWIDTH_PARTIAL=18 -D DSP_B_MAXWIDTH=18 " // Partial multipliers are intentionally "-D DSP_A_MAXWIDTH_PARTIAL=18 -D DSP_B_MAXWIDTH=18 " // Partial multipliers are intentionally