diff --git a/kernel/rtlil.h b/kernel/rtlil.h
index 1c7eaec39..c81990f43 100644
--- a/kernel/rtlil.h
+++ b/kernel/rtlil.h
@@ -1332,10 +1332,8 @@ struct RTLIL::Design
 	}
 
 
-	std::vector<RTLIL::Module*> selected_modules(RTLIL::SelectPartials partials, RTLIL::SelectBoxes boxes = SB_ALL) const;
+	std::vector<RTLIL::Module*> selected_modules(RTLIL::SelectPartials partials = SELECT_ALL, RTLIL::SelectBoxes boxes = SB_UNBOXED_WARN) const;
 
-	[[deprecated("Use selected_unboxed_modules() to maintain prior behaviour, or consider one of the other selected module helpers.")]]
-	std::vector<RTLIL::Module*> selected_modules() const { return selected_modules(SELECT_ALL, SB_UNBOXED_WARN); }
 	std::vector<RTLIL::Module*> all_selected_modules() const { return selected_modules(SELECT_ALL, SB_ALL); }
 	std::vector<RTLIL::Module*> selected_unboxed_modules() const { return selected_modules(SELECT_ALL, SB_UNBOXED_ONLY); }
 	std::vector<RTLIL::Module*> selected_unboxed_modules_warn() const { return selected_modules(SELECT_ALL, SB_UNBOXED_WARN); }
diff --git a/passes/opt/opt_clean.cc b/passes/opt/opt_clean.cc
index c37c03607..620b38813 100644
--- a/passes/opt/opt_clean.cc
+++ b/passes/opt/opt_clean.cc
@@ -734,7 +734,7 @@ struct CleanPass : public Pass {
 		count_rm_cells = 0;
 		count_rm_wires = 0;
 
-		for (auto module : design->selected_whole_modules()) {
+		for (auto module : design->selected_unboxed_whole_modules()) {
 			if (module->has_processes())
 				continue;
 			rmunused_module(module, purge_mode, ys_debug(), true);
diff --git a/passes/sat/sim.cc b/passes/sat/sim.cc
index 8fac93b98..dd2f1d255 100644
--- a/passes/sat/sim.cc
+++ b/passes/sat/sim.cc
@@ -2887,7 +2887,7 @@ struct SimPass : public Pass {
 			if (!top_mod)
 				log_cmd_error("Design has no top module, use the 'hierarchy' command to specify one.\n");
 		} else {
-			auto mods = design->selected_whole_modules();
+			auto mods = design->selected_unboxed_whole_modules();
 			if (GetSize(mods) != 1)
 				log_cmd_error("Only one top module must be selected.\n");
 			top_mod = mods.front();
@@ -3016,7 +3016,7 @@ struct Fst2TbPass : public Pass {
 			if (!top_mod)
 				log_cmd_error("Design has no top module, use the 'hierarchy' command to specify one.\n");
 		} else {
-			auto mods = design->selected_whole_modules();
+			auto mods = design->selected_unboxed_whole_modules();
 			if (GetSize(mods) != 1)
 				log_cmd_error("Only one top module must be selected.\n");
 			top_mod = mods.front();
diff --git a/passes/techmap/clockgate.cc b/passes/techmap/clockgate.cc
index 52851d922..3a3d24c0f 100644
--- a/passes/techmap/clockgate.cc
+++ b/passes/techmap/clockgate.cc
@@ -333,7 +333,7 @@ struct ClockgatePass : public Pass {
 		dict<ClkNetInfo, GClkNetInfo> clk_nets;
 
 		int gated_flop_count = 0;
-		for (auto module : design->selected_whole_modules()) {
+		for (auto module : design->selected_unboxed_whole_modules()) {
 			for (auto cell : module->cells()) {
 				if (!RTLIL::builtin_ff_cell_types().count(cell->type))
 					continue;