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Fix muxAB logic

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This commit is contained in:
Eddie Hung 2019-07-23 14:52:14 -07:00
parent 0dd2a125f6
commit a37574ccbf
1 changed files with 2 additions and 3 deletions
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5
passes/pmgen/ice40_dsp.pmg
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@ -187,10 +187,9 @@ code clock clock_pol sigO sigCD sigCD_signed
// Loading value into output register is not
// supported unless using accumulator
if (muxAB && sigCD != sigO) {
if (muxAB != addAB)
if (muxAB) {
if (sigCD != sigO)
reject;
if (muxA)
sigCD = port(muxAB, \B);
else if (muxB)