mirrors/yosys
3
0
Fork 0
mirror of https://github.com/YosysHQ/yosys synced 2026-01-04 18:18:52 +00:00
Code Activity

Merge 18a7d4c262 into 09f9e0e8d1

Browse source
This commit is contained in:
KrystalDelusion 2025-12-23 14:02:58 +01:00 • committed by GitHub
commit a3710bf1b5
No known key found for this signature in database
GPG key ID: B5690EEEBB952194
1 changed files with 3 additions and 0 deletions
Download patch file Download diff file Expand all files Collapse all files

3
docs/source/using_yosys/verilog.rst
View file

@ -355,6 +355,9 @@ from SystemVerilog:
design with `read_verilog`, all its packages are available to SystemVerilog
files being read into the same design afterwards.
- nested packages are currently not supported (i.e. calling ``import`` inside
a ``package`` .. ``endpackage`` block)
- typedefs are supported (including inside packages)
- type casts are currently not supported