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Added help messages for fsm_* passes
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10 changed files with 194 additions and 42 deletions
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@ -188,7 +188,7 @@ struct FsmExpand
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fsm_data.copy_to_cell(fsm_cell);
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}
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FsmExpand(RTLIL::Cell *cell, RTLIL::Module *mod)
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FsmExpand(RTLIL::Cell *cell, RTLIL::Design *design, RTLIL::Module *mod)
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{
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module = mod;
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fsm_cell = cell;
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@ -198,7 +198,7 @@ struct FsmExpand
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for (auto &cell_it : module->cells) {
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RTLIL::Cell *c = cell_it.second;
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if (ct.cell_known(c->type))
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if (ct.cell_known(c->type) && design->selected(mod, c))
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for (auto &p : c->connections) {
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if (ct.cell_output(c->type, p.first))
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sig2driver.insert(assign_map(p.second), c);
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@ -234,19 +234,32 @@ struct FsmExpand
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};
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struct FsmExpandPass : public Pass {
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FsmExpandPass() : Pass("fsm_expand") { }
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FsmExpandPass() : Pass("fsm_expand", "expand FSM cells by merging logic into it") { }
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virtual void help()
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{
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// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
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log("\n");
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log(" fsm_expand [selection]\n");
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log("\n");
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log("The fsm_extract pass is conservative about the cells that belong the a finate\n");
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log("state machine. This pass can be used to merge additional auxiliary gates into\n");
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log("the finate state machine.\n");
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log("\n");
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}
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virtual void execute(std::vector<std::string> args, RTLIL::Design *design)
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{
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log_header("Executing FSM_EXPAND pass (re-assigning FSM state encoding).\n");
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log_header("Executing FSM_EXPAND pass (merging auxiliary logic into FSMs).\n");
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extra_args(args, 1, design);
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for (auto &mod_it : design->modules) {
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if (!design->selected(mod_it.second))
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continue;
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std::vector<RTLIL::Cell*> fsm_cells;
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for (auto &cell_it : mod_it.second->cells)
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if (cell_it.second->type == "$fsm")
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if (cell_it.second->type == "$fsm" && design->selected(mod_it.second, cell_it.second))
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fsm_cells.push_back(cell_it.second);
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for (auto c : fsm_cells) {
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FsmExpand fsm_expand(c, mod_it.second);
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FsmExpand fsm_expand(c, design, mod_it.second);
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fsm_expand.execute();
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}
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}
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