mirrors/yosys
3
0
Fork 0
mirror of https://github.com/YosysHQ/yosys synced 2025-04-13 04:28:18 +00:00
Code Activity

Fix handling of task output ports in clocked always blocks, fixes #857

Browse source 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
This commit is contained in:
Clifford Wolf 2019-03-07 22:44:37 -08:00
parent 350dfd3745
commit a330c68363
2 changed files with 38 additions and 16 deletions
Show stats Download patch file Download diff file Expand all files Collapse all files

27
frontends/ast/simplify.cc
View file

@ -2224,6 +2224,8 @@ skip_dynamic_range_lvalue_expansion:;
std::map<std::string, std::string> replace_rules; std::map<std::string, std::string> replace_rules;
vector<AstNode*> added_mod_children; vector<AstNode*> added_mod_children;
dict<std::string, AstNode*> wire_cache; dict<std::string, AstNode*> wire_cache;
vector<AstNode*> new_stmts;
vector<AstNode*> output_assignments;
if (current_block == NULL) if (current_block == NULL)
{ {
@ -2348,7 +2350,7 @@ skip_dynamic_range_lvalue_expansion:;
wire->port_id = 0; wire->port_id = 0;
wire->is_input = false; wire->is_input = false;
wire->is_output = false; wire->is_output = false;
if (!child->is_output) wire->is_reg = true;
wire->attributes["\\nosync"] = AstNode::mkconst_int(1, false); wire->attributes["\\nosync"] = AstNode::mkconst_int(1, false);
wire_cache[child->str] = wire; wire_cache[child->str] = wire;
@ -2371,13 +2373,10 @@ skip_dynamic_range_lvalue_expansion:;
new AstNode(AST_ASSIGN_EQ, wire_id, arg) : new AstNode(AST_ASSIGN_EQ, wire_id, arg) :
new AstNode(AST_ASSIGN_EQ, arg, wire_id); new AstNode(AST_ASSIGN_EQ, arg, wire_id);
assign->children[0]->was_checked = true; assign->children[0]->was_checked = true;
if (child->is_input)
for (auto it = current_block->children.begin(); it != current_block->children.end(); it++) { new_stmts.push_back(assign);
if (*it != current_block_child) else
continue; output_assignments.push_back(assign);
current_block->children.insert(it, assign);
break;
}
} }
} }
@ -2391,11 +2390,15 @@ skip_dynamic_range_lvalue_expansion:;
{ {
AstNode *stmt = child->clone(); AstNode *stmt = child->clone();
stmt->replace_ids(prefix, replace_rules); stmt->replace_ids(prefix, replace_rules);
new_stmts.push_back(stmt);
}
for (auto it = current_block->children.begin(); it != current_block->children.end(); it++) { new_stmts.insert(new_stmts.end(), output_assignments.begin(), output_assignments.end());
if (*it != current_block_child)
continue; for (auto it = current_block->children.begin(); ; it++) {
current_block->children.insert(it, stmt); log_assert(it != current_block->children.end());
if (*it == current_block_child) {
current_block->children.insert(it, new_stmts.begin(), new_stmts.end());
break; break;
} }
} }

19
tests/simple/task_func.v
View file

@ -120,3 +120,22 @@ module task_func_test04(input [7:0] in, output [7:0] out1, out2, out3, out4);
assign out3 = test3(in); assign out3 = test3(in);
assign out4 = test4(in); assign out4 = test4(in);
endmodule endmodule
// -------------------------------------------------------------------
// https://github.com/YosysHQ/yosys/issues/857
module task_func_test05(data_in,data_out,clk);
output reg data_out;
input data_in;
input clk;
task myTask;
output out;
input in;
out = in;
endtask
always @(posedge clk) begin
myTask(data_out,data_in);
end
endmodule