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intel_alm: preliminary Arria V support

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Lofty 2021-11-24 21:20:40 +00:00 • committed by Marcelina Kościelnicka
parent 77327b2544
commit a31c8a82be
6 changed files with 199 additions and 7 deletions
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50
techlibs/intel_alm/common/mem_sim.v
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@ -56,6 +56,33 @@ module MISTRAL_MLAB(input [4:0] A1ADDR, input A1DATA, A1EN,
reg [31:0] mem = 32'b0;
`ifdef cyclonev
specify
$setup(A1ADDR, posedge CLK1, 86);
$setup(A1DATA, posedge CLK1, 86);
$setup(A1EN, posedge CLK1, 86);
(B1ADDR[0] => B1DATA) = 487;
(B1ADDR[1] => B1DATA) = 475;
(B1ADDR[2] => B1DATA) = 382;
(B1ADDR[3] => B1DATA) = 284;
(B1ADDR[4] => B1DATA) = 96;
endspecify
`endif
`ifdef arriav
specify
$setup(A1ADDR, posedge CLK1, 62);
$setup(A1DATA, posedge CLK1, 62);
$setup(A1EN, posedge CLK1, 62);
(B1ADDR[0] => B1DATA) = 370;
(B1ADDR[1] => B1DATA) = 292;
(B1ADDR[2] => B1DATA) = 218;
(B1ADDR[3] => B1DATA) = 74;
(B1ADDR[4] => B1DATA) = 177;
endspecify
`endif
`ifdef cyclone10gx
// TODO: Cyclone 10 GX timings; the below timings are for Cyclone V
specify
$setup(A1ADDR, posedge CLK1, 86);
@ -68,6 +95,7 @@ specify
(B1ADDR[3] => B1DATA) = 284;
(B1ADDR[4] => B1DATA) = 96;
endspecify
`endif
always @(posedge CLK1)
if (A1EN) mem[A1ADDR] <= A1DATA;
@ -93,12 +121,28 @@ output reg [CFG_DBITS-1:0] B1DATA;
reg [2**CFG_ABITS * CFG_DBITS - 1 : 0] mem = 0;
`ifdef cyclonev
specify
$setup(A1ADDR, posedge CLK1, 0);
$setup(A1DATA, posedge CLK1, 0);
$setup(A1ADDR, posedge CLK1, 125);
$setup(A1DATA, posedge CLK1, 97);
$setup(A1EN, posedge CLK1, 140);
$setup(B1ADDR, posedge CLK1, 125);
$setup(B1EN, posedge CLK1, 161);
if (B1EN) (posedge CLK1 => (B1DATA : A1DATA)) = 0;
if (B1EN) (posedge CLK1 => (B1DATA : A1DATA)) = 1004;
endspecify
`endif
`ifdef arriav
specify
$setup(A1ADDR, posedge CLK1, 97);
$setup(A1DATA, posedge CLK1, 74);
$setup(A1EN, posedge CLK1, 109);
$setup(B1ADDR, posedge CLK1, 97);
$setup(B1EN, posedge CLK1, 126);
if (B1EN) (posedge CLK1 => (B1DATA : A1DATA)) = 787;
endspecify
`endif
always @(posedge CLK1) begin
if (A1EN)