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intel_alm: preliminary Arria V support

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Lofty 2021-11-24 21:20:40 +00:00 • committed by Marcelina Kościelnicka
parent 77327b2544
commit a31c8a82be
6 changed files with 199 additions and 7 deletions
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47
techlibs/intel_alm/common/dsp_sim.v
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@ -1,14 +1,31 @@
`default_nettype none
(* abc9_box *)
module MISTRAL_MUL27X27(input [26:0] A, input [26:0] B, output [53:0] Y);
parameter A_SIGNED = 1;
parameter B_SIGNED = 1;
`ifdef cyclonev
specify
(A *> Y) = 3732;
(B *> Y) = 3928;
endspecify
`endif
`ifdef arriav
// NOTE: Arria V appears to have only one set of timings for all DSP modes...
specify
(A *> Y) = 1895;
(B *> Y) = 2053;
endspecify
`endif
`ifdef cyclone10gx
// TODO: Cyclone 10 GX timings; the below are for Cyclone V
specify
(A *> Y) = 3732;
(B *> Y) = 3928;
endspecify
`endif
wire [53:0] A_, B_;
@ -32,11 +49,26 @@ module MISTRAL_MUL18X18(input [17:0] A, input [17:0] B, output [35:0] Y);
parameter A_SIGNED = 1;
parameter B_SIGNED = 1;
`ifdef cyclonev
specify
(A *> Y) = 3180;
(B *> Y) = 3982;
endspecify
`endif
`ifdef arriav
// NOTE: Arria V appears to have only one set of timings for all DSP modes...
specify
(A *> Y) = 1895;
(B *> Y) = 2053;
endspecify
`endif
`ifdef cyclone10gx
// TODO: Cyclone 10 GX timings; the below are for Cyclone V
specify
(A *> Y) = 3180;
(B *> Y) = 3982;
endspecify
`endif
wire [35:0] A_, B_;
@ -60,11 +92,26 @@ module MISTRAL_MUL9X9(input [8:0] A, input [8:0] B, output [17:0] Y);
parameter A_SIGNED = 1;
parameter B_SIGNED = 1;
`ifdef cyclonev
specify
(A *> Y) = 2818;
(B *> Y) = 3051;
endspecify
`endif
`ifdef arriav
// NOTE: Arria V appears to have only one set of timings for all DSP modes...
specify
(A *> Y) = 1895;
(B *> Y) = 2053;
endspecify
`endif
`ifdef cyclone10gx
// TODO: Cyclone 10 GX timings; the below are for Cyclone V
specify
(A *> Y) = 2818;
(B *> Y) = 3051;
endspecify
`endif
wire [17:0] A_, B_;