mirrors/yosys
3
0
Fork 0
mirror of https://github.com/YosysHQ/yosys synced 2025-11-04 13:29:12 +00:00
Code Activity

Short out async box

Browse source
This commit is contained in:
Eddie Hung 2019-07-11 10:52:45 -07:00
parent 8fef4c3594
commit a314565ad4
1 changed files with 14 additions and 0 deletions
Download patch file Download diff file Expand all files Collapse all files

14
frontends/aiger/aigerparse.cc
View file

@ -741,6 +741,9 @@ void AigerReader::parse_aiger_binary()
void AigerReader::post_process() void AigerReader::post_process()
{ {
const RTLIL::Wire* n0 = module->wire("\\__0__");
const RTLIL::Wire* n1 = module->wire("\\__1__");
pool<IdString> seen_boxes; pool<IdString> seen_boxes;
dict<IdString, RTLIL::Module*> flop_data; dict<IdString, RTLIL::Module*> flop_data;
unsigned ci_count = 0, co_count = 0, flop_count = 0; unsigned ci_count = 0, co_count = 0, flop_count = 0;
@ -847,6 +850,17 @@ void AigerReader::post_process()
flop_count++; flop_count++;
cell->type = flop_module->name; cell->type = flop_module->name;
module->connect(q, d); module->connect(q, d);
continue;
}
// Remove the async mux by shorting out its input and output
if (cell->type == "$__ABC_ASYNC") {
RTLIL::Wire* A = cell->getPort("\\A").as_wire();
if (A == n0 || A == n1) A = nullptr;
auto it = cell->connections_.find("\\Y");
log_assert(it != cell->connections_.end());
module->connect(it->second, A);
cell->connections_.erase(it);
} }
} }