mirror of
https://github.com/YosysHQ/yosys
synced 2025-10-31 03:32:29 +00:00
Dan Ravensloft
Marcelina Kościelnicka
parent
62311b7ec0
commit
a2fb84fd0c
8 changed files with 133 additions and 39 deletions
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@ -15,9 +15,9 @@ $(eval $(call add_share_file,share/intel_alm/common,techlibs/intel_alm/common/ds
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$(eval $(call add_share_file,share/intel_alm/common,techlibs/intel_alm/common/mem_sim.v))
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# RAM
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bramtypes := m10k m20k
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$(foreach bramtype, $(bramtypes), $(eval $(call add_share_file,share/intel_alm/common,techlibs/intel_alm/common/bram_$(bramtype).txt)))
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$(foreach bramtype, $(bramtypes), $(eval $(call add_share_file,share/intel_alm/common,techlibs/intel_alm/common/bram_$(bramtype)_map.v)))
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$(eval $(call add_share_file,share/intel_alm/common,techlibs/intel_alm/common/bram_m10k.txt))
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$(eval $(call add_share_file,share/intel_alm/common,techlibs/intel_alm/common/bram_m20k.txt))
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$(eval $(call add_share_file,share/intel_alm/common,techlibs/intel_alm/common/bram_m20k_map.v))
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$(eval $(call add_share_file,share/intel_alm/common,techlibs/intel_alm/common/lutram_mlab.txt))
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# Miscellaneous
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@ -1,4 +1,4 @@
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bram __MISTRAL_M10K_SDP
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bram MISTRAL_M10K
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init 0 # TODO: Re-enable when I figure out how BRAM init works
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abits 13 @D8192x1
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dbits 1 @D8192x1
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@ -27,7 +27,7 @@ bram __MISTRAL_M10K_SDP
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endbram
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match __MISTRAL_M10K_SDP
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match MISTRAL_M10K
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min efficiency 5
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make_transp
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endmatch
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@ -1,31 +0,0 @@
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module __MISTRAL_M10K_SDP(CLK1, A1ADDR, A1DATA, A1EN, B1ADDR, B1DATA, B1EN);
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parameter CFG_ABITS = 10;
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parameter CFG_DBITS = 10;
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parameter CFG_ENABLE_A = 1;
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parameter CFG_ENABLE_B = 1;
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input CLK1;
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input [CFG_ABITS-1:0] A1ADDR, B1ADDR;
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input [CFG_DBITS-1:0] A1DATA;
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output [CFG_DBITS-1:0] B1DATA;
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input [CFG_ENABLE_A-1:0] A1EN, B1EN;
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altsyncram #(
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.operation_mode("dual_port"),
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.ram_block_type("m10k"),
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.widthad_a(CFG_ABITS),
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.width_a(CFG_DBITS),
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.widthad_b(CFG_ABITS),
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.width_b(CFG_DBITS),
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) _TECHMAP_REPLACE_ (
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.address_a(A1ADDR),
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.data_a(A1DATA),
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.wren_a(A1EN),
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.address_b(B1ADDR),
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.q_b(B1DATA),
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.clock0(CLK1),
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.clock1(CLK1)
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);
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endmodule
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@ -157,3 +157,38 @@ input [ay_scan_in_width-1:0] ay;
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output [result_a_width-1:0] resulta;
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endmodule
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(* blackbox *)
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module cyclonev_ram_block(portaaddr, portadatain, portawe, portbaddr, portbdataout, portbre, clk0);
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parameter operation_mode = "dual_port";
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parameter logical_ram_name = "";
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parameter port_a_address_width = 10;
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parameter port_a_data_width = 10;
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parameter port_a_logical_ram_depth = 1024;
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parameter port_a_logical_ram_width = 10;
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parameter port_a_first_address = 0;
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parameter port_a_last_address = 1023;
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parameter port_a_first_bit_number = 0;
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parameter port_b_address_width = 10;
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parameter port_b_data_width = 10;
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parameter port_b_logical_ram_depth = 1024;
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parameter port_b_logical_ram_width = 10;
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parameter port_b_first_address = 0;
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parameter port_b_last_address = 1023;
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parameter port_b_first_bit_number = 0;
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parameter port_b_address_clock = "clock0";
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parameter port_b_read_enable_clock = "clock0";
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parameter mem_init0 = "";
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parameter mem_init1 = "";
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parameter mem_init2 = "";
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parameter mem_init3 = "";
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parameter mem_init4 = "";
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input [port_a_address_width-1:0] portaaddr;
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input [port_b_address_width-1:0] portbaddr;
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input [port_a_data_width-1:0] portadatain;
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output [port_b_data_width-1:0] portbdataout;
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input clk0, portawe, portbre;
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endmodule
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@ -73,3 +73,37 @@ always @(posedge CLK1)
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assign B1DATA = mem[B1ADDR];
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endmodule
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// The M10K
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// --------
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// TODO
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module MISTRAL_M10K(CLK1, A1ADDR, A1DATA, A1EN, B1ADDR, B1DATA, B1EN);
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parameter CFG_ABITS = 10;
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parameter CFG_DBITS = 10;
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input CLK1;
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input [CFG_ABITS-1:0] A1ADDR, B1ADDR;
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input [CFG_DBITS-1:0] A1DATA;
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input A1EN, B1EN;
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output reg [CFG_DBITS-1:0] B1DATA;
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reg [2**CFG_ABITS * CFG_DBITS - 1 : 0] mem = 0;
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specify
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$setup(A1ADDR, posedge CLK1, 0);
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$setup(A1DATA, posedge CLK1, 0);
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if (B1EN) (posedge CLK1 => (B1DATA : A1DATA)) = 0;
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endspecify
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always @(posedge CLK1) begin
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if (A1EN)
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mem[(A1ADDR + 1) * CFG_DBITS - 1 : A1ADDR * CFG_DBITS] <= A1DATA;
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if (B1EN)
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B1DATA <= mem[(B1ADDR + 1) * CFG_DBITS - 1 : B1ADDR * CFG_DBITS];
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end
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endmodule
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@ -88,6 +88,8 @@ endmodule
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module MISTRAL_MLAB(input [4:0] A1ADDR, input A1DATA, A1EN, CLK1, input [4:0] B1ADDR, output B1DATA);
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parameter _TECHMAP_CELLNAME_ = "";
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// Here we get to an unfortunate situation. The cell has a mem_init0 parameter,
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// which takes in a hexadecimal string that could be used to initialise RAM.
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// In the vendor simulation models, this appears to work fine, but Quartus,
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@ -99,7 +101,7 @@ module MISTRAL_MLAB(input [4:0] A1ADDR, input A1DATA, A1EN, CLK1, input [4:0] B1
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// or an undocumented way to get Quartus to initialise from mem_init0 is found.
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`MLAB #(
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.logical_ram_name("MISTRAL_MLAB"),
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.logical_ram_name(_TECHMAP_CELLNAME_),
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.logical_ram_depth(32),
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.logical_ram_width(1),
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.mixed_port_feed_through_mode("Dont Care"),
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@ -123,6 +125,53 @@ module MISTRAL_MLAB(input [4:0] A1ADDR, input A1DATA, A1EN, CLK1, input [4:0] B1
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endmodule
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module MISTRAL_M10K(A1ADDR, A1DATA, A1EN, CLK1, B1ADDR, B1DATA, B1EN);
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parameter CFG_ABITS = 10;
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parameter CFG_DBITS = 10;
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parameter _TECHMAP_CELLNAME_ = "";
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input [CFG_ABITS-1:0] A1ADDR, B1ADDR;
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input [CFG_DBITS-1:0] A1DATA;
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input CLK1, A1EN, B1EN;
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output [CFG_DBITS-1:0] B1DATA;
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// Much like the MLAB, the M10K has mem_init[01234] parameters which would let
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// you initialise the RAM cell via hex literals. If they were implemented.
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cyclonev_ram_block #(
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.operation_mode("dual_port"),
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.logical_ram_name(_TECHMAP_CELLNAME_),
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.port_a_address_width(CFG_ABITS),
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.port_a_data_width(CFG_DBITS),
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.port_a_logical_ram_depth(2**CFG_ABITS),
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.port_a_logical_ram_width(CFG_DBITS),
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.port_a_first_address(0),
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.port_a_last_address(2**CFG_ABITS - 1),
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.port_a_first_bit_number(0),
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.port_b_address_width(CFG_ABITS),
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.port_b_data_width(CFG_DBITS),
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.port_b_logical_ram_depth(2**CFG_ABITS),
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.port_b_logical_ram_width(CFG_DBITS),
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.port_b_first_address(0),
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.port_b_last_address(2**CFG_ABITS - 1),
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.port_b_first_bit_number(0),
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.port_b_address_clock("clock0"),
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.port_b_read_enable_clock("clock0")
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) _TECHMAP_REPLACE_ (
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.portaaddr(A1ADDR),
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.portadatain(A1DATA),
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.portawe(A1EN),
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.portbaddr(B1ADDR),
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.portbdataout(B1DATA),
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.portbre(B1EN),
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.clk0(CLK1)
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);
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endmodule
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module MISTRAL_MUL27X27(input [26:0] A, B, output [53:0] Y);
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`MAC #(.ax_width(27), .ay_scan_in_width(27), .result_a_width(54), .operation_mode("M27x27")) _TECHMAP_REPLACE_ (.ax(A), .ay(B), .resulta(Y));
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@ -235,6 +235,7 @@ struct SynthIntelALMPass : public ScriptPass {
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if (!nobram && check_label("map_bram", "(skip if -nobram)")) {
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run(stringf("memory_bram -rules +/intel_alm/common/bram_%s.txt", bram_type.c_str()));
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if (help_mode || bram_type != "m10k")
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run(stringf("techmap -map +/intel_alm/common/bram_%s_map.v", bram_type.c_str()));
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}
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6
tests/arch/intel_alm/blockram.ys
Normal file
6
tests/arch/intel_alm/blockram.ys
Normal file
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@ -0,0 +1,6 @@
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read_verilog ../common/blockram.v
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chparam -set ADDRESS_WIDTH 10 -set DATA_WIDTH 10 sync_ram_sdp
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synth_intel_alm -family cyclonev
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cd sync_ram_sdp
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select -assert-count 1 t:MISTRAL_M10K
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select -assert-none t:MISTRAL_M10K %% t:* %D
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