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https://github.com/YosysHQ/yosys
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cellhelp: Add source line to help
Include Source file and line number in SimHelper struct, and use it for verilog code caption in rst dump. Also reformat python string conversion to iterate over a list of fields instead of repeating code for each.
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784292626e
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2 changed files with 18 additions and 7 deletions
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@ -3,11 +3,13 @@
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from __future__ import annotations
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import fileinput
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import json
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from pathlib import Path
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class SimHelper:
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name: str = ""
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title: str = ""
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ports: str = ""
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source: str = ""
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desc: list[str]
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code: list[str]
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ver: str = "1"
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@ -16,14 +18,19 @@ class SimHelper:
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self.desc = []
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def __str__(self) -> str:
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printed_fields = [
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"name", "title", "ports", "source", "desc", "code", "ver",
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]
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# generate C++ struct
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val = "tempCell = {\n"
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val += f' {json.dumps(self.name)},\n'
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val += f' {json.dumps(self.title)},\n'
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val += f' {json.dumps(self.ports)},\n'
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val += ' ' + json.dumps("\n".join(self.desc)) + ',\n'
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val += ' ' + json.dumps("\n".join(self.code)) + ',\n'
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val += f' {json.dumps(self.ver)},\n'
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for field in printed_fields:
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field_val = getattr(self, field)
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if isinstance(field_val, list):
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field_val = "\n".join(field_val)
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val += f' {json.dumps(field_val)},\n'
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val += "};\n"
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# map name to struct
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val += f'cell_help[{json.dumps(self.name)}] = tempCell;'
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val += "\n"
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val += f'cell_code[{json.dumps(self.name + "+")}] = tempCell;'
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@ -45,6 +52,8 @@ for line in fileinput.input():
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clean_line = line[7:].replace("\\", "").replace(";", "")
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simHelper.name, simHelper.ports = clean_line.split(maxsplit=1)
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simHelper.code = []
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short_filename = Path(fileinput.filename()).name
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simHelper.source = f'{short_filename}:{fileinput.filelineno()}'
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elif not line.startswith("endmodule"):
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line = " " + line
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try:
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