mirrors/yosys
3
0
Fork 0
mirror of https://github.com/YosysHQ/yosys synced 2025-11-12 00:52:05 +00:00
Code Activity

Merge pull request #5461 from rocallahan/reset-abc-config

Browse source 
Fix regression in configuring ABC techmapping
This commit is contained in:
Emil J 2025-11-06 11:58:04 +01:00 • committed by GitHub
commit a2aeef6c96
No known key found for this signature in database
GPG key ID: B5690EEEBB952194
2 changed files with 80 additions and 56 deletions
Download patch file Download diff file Expand all files Collapse all files

26
tests/techmap/abc_state.ys Normal file
View file

@ -0,0 +1,26 @@
read_verilog <<EOT
module simple(I1, I2, O);
input wire I1;
input wire I2;
output wire O;
assign O = I1 | I2;
endmodule
EOT
abc -g all
design -reset
read_verilog <<EOT
module simple(I1, I2, O);
input wire I1;
input wire I2;
output wire O;
assign O = I1 | I2;
endmodule
EOT
techmap
abc -g AND
select -assert-count 0 t:$_OR_
select -assert-count 1 t:$_AND_