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https://github.com/YosysHQ/yosys
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design: properly switch signorm mode when restoring saved designs
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1 changed files with 3 additions and 0 deletions
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@ -359,6 +359,8 @@ struct DesignPass : public Pass {
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if (reset_mode || !load_name.empty() || push_mode || pop_mode)
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if (reset_mode || !load_name.empty() || push_mode || pop_mode)
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{
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{
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design->flagSigNormalized = false;
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for (auto mod : design->modules().to_vector())
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for (auto mod : design->modules().to_vector())
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design->remove(mod);
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design->remove(mod);
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@ -380,6 +382,7 @@ struct DesignPass : public Pass {
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{
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{
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RTLIL::Design *saved_design = pop_mode ? pushed_designs.back() : saved_designs.at(load_name);
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RTLIL::Design *saved_design = pop_mode ? pushed_designs.back() : saved_designs.at(load_name);
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design->flagSigNormalized = saved_design->flagSigNormalized;
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for (auto mod : saved_design->modules())
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for (auto mod : saved_design->modules())
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design->add(mod->clone());
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design->add(mod->clone());
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