From a27378cff8404ed46d2cc2177b8d6a52e86cbf1e Mon Sep 17 00:00:00 2001
From: "Emil J. Tywoniak" <emil@tywoniak.eu>
Date: Mon, 3 Aug 2026 15:55:22 +0200
Subject: [PATCH] hierarchy: regression test for keep cache

---
 tests/various/hierarchy_recursive.v  |  3 +++
 tests/various/hierarchy_recursive.ys | 25 +++++++++++++++++++++++++
 2 files changed, 28 insertions(+)
 create mode 100644 tests/various/hierarchy_recursive.v
 create mode 100644 tests/various/hierarchy_recursive.ys

diff --git a/tests/various/hierarchy_recursive.v b/tests/various/hierarchy_recursive.v
new file mode 100644
index 000000000..9d4fd323c
--- /dev/null
+++ b/tests/various/hierarchy_recursive.v
@@ -0,0 +1,3 @@
+module top(input x, output y);
+top top_i(.x(x), .y(y));
+endmodule
\ No newline at end of file
diff --git a/tests/various/hierarchy_recursive.ys b/tests/various/hierarchy_recursive.ys
new file mode 100644
index 000000000..e9f203828
--- /dev/null
+++ b/tests/various/hierarchy_recursive.ys
@@ -0,0 +1,25 @@
+read_verilog hierarchy_recursive.v
+hierarchy -auto-top
+select -assert-any top
+select -assert-none a:keep
+
+design -reset
+read_verilog <<EOT
+module top(input x, output y);
+top top_i(.x(x), .y(y));
+always @(x) $display("x=%d", x);
+endmodule
+EOT
+hierarchy -auto-top
+select -assert-any top %% a:keep
+
+design -reset
+read_verilog -formal <<EOT
+module a(input x); b b_i(.x(x)); endmodule
+module b(input x); a a_i(.x(x)); always @(x) assert (x == x); endmodule
+module top(input x); a a_i(.x(x)); endmodule
+EOT
+hierarchy -top top
+select -assert-any a %% a:keep
+select -assert-any b %% a:keep
+select -assert-any top %% a:keep