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Put abc_* attributes above port

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This commit is contained in:
Eddie Hung 2019-08-23 11:21:44 -07:00
parent bb2d5bc4f8
commit a270af00cc
3 changed files with 28 additions and 14 deletions
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6
techlibs/ice40/cells_sim.v
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@ -143,11 +143,13 @@ endmodule
(* abc_box_id = 1, lib_whitebox *)
module \$__ICE40_FULL_ADDER (
(* abc_carry *) output CO,
(* abc_carry *)
output CO,
output O,
input A,
input B,
(* abc_carry *) input CI
(* abc_carry *)
input CI
);
SB_CARRY carry (
.I0(A),